Community
cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Novice
276 Views

Error synthesizing Nios II design in Quartus 19.1

Jump to solution

I'm having a problem synthesizing Nios II design in Quartus 19.1 (or any 19.x version). I created a simple Nios II design with Platform Designer containing reset bridge, clock bridge, Nios II processor, On-chip memory (128KB) to store data/instruction, JTAG UART, and timer. I set the system qsys as the top entity and ran Analysis & Synthesis. It failed with the following errors

 

Error(13223): Verilog HDL or VHDL error: cannot open verilog file 'ip/test_nios_sys/test_nios_sys_nios2_gen2_0/altera_nios2_gen2_unit_191/synth/altera_nios2_gen2_rtl_module.sv'

Error(16045): Instance "nios2_gen2_0|nios2_gen2_0|cpu|the_nios2_rtl" instantiates undefined entity "altera_nios2_gen2_rtl_module"

Error(16185): Can't elaborate user hierarchy "nios2_gen2_0|nios2_gen2_0|cpu|the_nios2_rtl"

Error(16185): Can't elaborate user hierarchy "nios2_gen2_0|nios2_gen2_0|cpu"

Error(16185): Can't elaborate user hierarchy "nios2_gen2_0|nios2_gen2_0"

Error(16185): Can't elaborate user hierarchy "nios2_gen2_0"

Error(16186): Can't elaborate top-level user hierarchy

Error: Flow failed: 

Error: Quartus Prime Synthesis was unsuccessful. 8 errors, 1 warning

   Error: Peak virtual memory: 1552 megabytes

   Error: Processing ended: Mon Oct 28 11:54:45 2019

   Error: Elapsed time: 00:00:12

Error: Peak virtual memory: 1552 megabytes

Error: Processing ended: Mon Oct 28 11:54:45 2019

Error: Elapsed time: 00:00:12

 

I tried a couple of things:

 

-Deleted qdb folder and re-ran the tool but got the same result.

-Quartus 19.2 and 19.3 gave the same result.

-I applied patch 0.02 for 19.1 (not the same problem but it has to do with Nios II) and that didn't help (https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/tools/...).

-Nios II e version gave the same result.

-Windows 10 and CentOS 7 gave the same result.

-Quartus 18.1 had no problem synthesizing the same design.

 

For info, my Nios II license is "Nios II Embedded Process Encrypted output (00A2)". This shouldn't matter because I compiled design with this license before on older versions of Quartus.

 

Is this a known issue with 19.x version and is there a workaround?

0 Kudos

Accepted Solutions
Highlighted
Novice
10 Views

Re: Error synthesizing Nios II design in Quartus 19.1

Jump to solution

I think I figured out the problem. It has to do with FlexLM version. The alterad and lmgrd daemons running on the license server were old and had to be updated to v11.16.2. Thanks for responding.

View solution in original post

0 Kudos
3 Replies
Highlighted
Valued Contributor II
10 Views

Re: Error synthesizing Nios II design in Quartus 19.1

Jump to solution

After you create the NIOS design in Platform Designer, did you save and generate the system? If not, generate the system and then close Platform designer , compile the design and check. It should work. Also make sure that the location where you have saved and generated the system is in the Quartus main project folder and not in another location.

0 Kudos
Highlighted
Novice
10 Views

Re: Error synthesizing Nios II design in Quartus 19.1

Jump to solution

Yes, I did save and generate HDL and it didn't work. The qsys file is in the same quartus project directory (ip folder is also in there). The thing is that if I follow the path, the file is there. I just don't know why Quartus wouldn't pick it up. It's an encrypted file though. I'm not sure if this could be a problem with this version of Quartus.

0 Kudos
Highlighted
Novice
11 Views

Re: Error synthesizing Nios II design in Quartus 19.1

Jump to solution

I think I figured out the problem. It has to do with FlexLM version. The alterad and lmgrd daemons running on the license server were old and had to be updated to v11.16.2. Thanks for responding.

View solution in original post

0 Kudos