Error while simulating nios ii with custom component

[Altera_Forum]

Hello all, 

i want to simulate a Qsys system which contains nios ii and a custom peripheral. I created the testbench system in Verilog (Simple, BFMs for clocks and resets) and launch modelsim through Nios ii SBT for eclipse (Run as Modelsim). My application project consists of some registers' accesses from nios ii to the slave peripheral. I have also an interrupt handler. I post the code below. The result of includes some warnings, like  Time: 1194710000 Instance: nios_with_bloom_filter_tb.nios_with_bloom_filter_inst.onchip_memory.the_altsyncram.genblk1.altsyncram_inst# Warning : Address pointed at port A is out of bound!  and the simulation breaks with an error "ERROR: nios_with_bloom_filter_nios2_0_test_bench/M_en is 'x'". However, in my application project i can see a folder called "mem_init" where the initiliazation files are supposed to be. Before the error the message "Hello world" is printed (the first command of main) but only this, no registers are read. Moreover, if I type the aforementioned command (printf("Hello world\n");) somewhere else in the program the message is not typed in modelsim... Any suggestions...? # include "system.h"# include "io.h"# include <stdint.h># include <stdio.h># include <stdlib.h># include <unistd.h># include "sys/alt_irq.h"    void handle_my_interrupts1 (void* context, alt_u32 id){  uint32_t enable_direct1; uint32_t enable_delay1; uint32_t enable_direct2; uint32_t enable_delay2;   //read enable direct1  enable_direct1=IORD ( BLOOM_FILTER_STATE_MACHINE_2_SPUS_0_BASE, 0x3);   //read enable_delay1  enable_delay1=IORD ( BLOOM_FILTER_STATE_MACHINE_2_SPUS_0_BASE, 0x4);   //read enable direct1  enable_direct2=IORD ( BLOOM_FILTER_STATE_MACHINE_2_SPUS_0_BASE, 0x5);   //read enable_delay1  enable_delay2=IORD ( BLOOM_FILTER_STATE_MACHINE_2_SPUS_0_BASE, 0x6);       printf("Enable_direct1 is %u\n", enable_direct1);  printf("Enable_delay1 is %u\n", enable_delay1);  printf("Enable_direct2 is %u\n", enable_direct2);  printf("Enable_delay2 is %u\n", enable_delay2); }    int main() {      printf("Hello world\n");  //registering interrupt handler functions    alt_ic_isr_register(BLOOM_FILTER_STATE_MACHINE_2_SPUS_0_IRQ_INTERRUPT_CONTROLLER_ID, BLOOM_FILTER_STATE_MACHINE_2_SPUS_0_IRQ, handle_my_interrupts1, (void*) NULL, 0x0);     //registers access    IOWR( BLOOM_FILTER_STATE_MACHINE_2_SPUS_0_BASE, 0x0, 0x00001111);   IOWR( BLOOM_FILTER_STATE_MACHINE_2_SPUS_0_BASE ,0x1 , 0x00002EF7);   IOWR( BLOOM_FILTER_STATE_MACHINE_2_SPUS_0_BASE , 0x2, 0x00004ED7);   while(1)  {   } return 0; }

[Altera_Forum]

Updated... 

I tried running it without the interrupt handler and seems to work which means the problem is the interrupt. So, can't i simulate a custom component with interrupt?

[Altera_Forum]

Hello again, 

i finally made had the program run (the first command printf("Hello world\n"); seeme to cause the problem...). But i come across a different problem: among the 3 registers' accesses (IOWR) only the last one is "saved". It acts as if the prior ones are set to '0'... Isn't it weird taking into account that my design works perfectly in hardware?? Thank you.

[Altera_Forum]

Can you check your objdump to see whether the 3 IOWR gets compiled into assembly?