Nios® II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
12453 Discussions

Etherenet TCP/IP server for Arria V board

Honored Contributor II

I have an Arria V starter kit, which has an ethernet port on it. I was unable to find a tutorial on how to use the ethernet on that specific board, but I found a triple speed ethernet tutorial for DE2-115 boards. I created a nios II system which includes a triple speed ethernet according to this tutorial (see image)  


I connected the nios II system to the ethernet pins on the FPGA as described in the tutorial:  


I think I've done everything correctly. 


I'm following the NicheStack TCP/IP tutorial to setup a simple socket server (, but I think this may not be compatible with the Nios II system I generated.  


After setting up the BSP, I try to build the simple socket server and I get this error: 

In file included from ./HAL/inc/includes.h:23:0, 

from ./UCOSII/inc/priv/alt_sem_ucosii.h:45, 

from ./UCOSII/inc/os/alt_sem.h:75, 

from ./HAL/inc/priv/alt_file.h:44, 

from HAL/src/alt_close.c:37: 

./UCOSII/inc/ucos_ii.h:1708:2: error:# error "OS_CFG.H, Missing OS_TICKS_PER_SEC: Sets the number of ticks in one second" 

# error "OS_CFG.H, Missing OS_TICKS_PER_SEC: Sets the number of ticks in one second" 


I am unsure what to do. I have been unable to find any tutorials for my device. Is there a general etherenet / TCP/IP tutorial for Altera boards? My google searching has not produced anything helpful
0 Kudos
2 Replies
Honored Contributor II

I was able to solve the compile error I got by adding an interval timer to my nios II system, but now I'm getting another error when I compile: 


In file included from ./drivers/inc/iniche/altera_eth_tse_iniche.h:36:0, 

from ./drivers/inc/altera_eth_tse.h:36, 

from alt_sys_init.c:65: 

./drivers/inc/iniche/ins_tse_mac.h:34:27: fatal error: altera_msgdma.h: No such file or directory 


Note: I am running quartis and eclipese-nios on a scientific linux machine


I am trying to implement triple speed ethernet in nios processor using modular scatter gather dma (msgdma) controller. I have build the qsys. For memory i have used ram. I have called 2 msgdma one for receiving in streaming to memory mode and one for transmitting in memory to streaming mode. I have done the interconnections in qsys platform and generated the HDL successfully. The sopcinfo file is also generated. Using this sopcinfo file i tried to generate the bsp. The bsp generates but when i try to build the bsp project in eclipse the build fails. It says that " fatal error. altera_msgdma.h. No such file exists."

I am using Quartus 18.1. I cannot downgrade to lower version as i have progressed a lot in 18.1 and now cannot migrate to a lower version because of dependency issues.

Actually this file is missing in alt_avalon_tse.h. The altera_msgdma.h exists in the installation folder of quartus 18.1 in c drive. But some how when i try to build the bsp it doesn't pick that file and throws the above mentioned error. I have tried to manually move altera_msgdma.h and altera_msgdma.c file into the incude and source file of the driver folder of the project file. After doing this the bsp builds, but the actual project build fails.

I am not using linux

Kindly guide