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12419 Discussions

Ethernet TCP / UDP hardware implemation

Altera_Forum
Honored Contributor II
1,848 Views

Hello everyvbody, 

 

sorry for the mistake: Ethernet TCP / UDP hardware implementation 

 

I have to send data with a speed of 700MBit/s. I use a Gigabit Phy (Marvel) and a gigabit mac-core (MTIP). Using LWIP is to slow (only 3-5MBit/s) in RAW mode. So my question: 

 

Is there anybody who has an idea how to implement a (UDP) packet generator for VHDL? This issnt a simple problem I know. TCP is too complex I think, so TCP stuff is done by LWIP. The speed is ok, TCP is only needed for some control packets. 

 

brainstorming: 

 

DataSource(16Bit or 32Bit) ----> Blackbox UDP generator ----> UDP Packet with UDP/IP Header ----> MAC ----> PHY 

 

Hope anyone has an idea or some stuff to read. 

 

Greetings 

 

http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/wink.gif [/B]
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6 Replies
Altera_Forum
Honored Contributor II
136 Views

UDP is pretty simple, especially if you can just have some configurable registers in your HW that dump in destination MAC, IP, port, etc. The challenge is getting the checksum done properly. Are you using the MTIP mac that can calculate checksums in place once the packets is sent for transmission? If so you won&#39;t need to worry about it.. If you do need to resolve checksums yourself, you&#39;ll need to have your HDL examine the entire contents of the packet prior to transmission, which means fast RAM... a common implementation is a DMA engine integrated into your custom logic that can be used to examine memory. Sounds like a fun project!

Altera_Forum
Honored Contributor II
136 Views

Hello CReal, 

 

Altera has got two reference designs which could be interested for you: 

 

nios ii network acceleration reference design (http://www.altera.com/end-markets/refdesigns/sys-sol/computing/ref-accel-network.html

video over ip reference design (http://www.altera.com/end-markets/refdesigns/sys-sol/broadcast/ref-video.html

 

Regards, 

niosIIuser
Altera_Forum
Honored Contributor II
136 Views

Hello again! 

 

I had some email contact with "InterNiche". They have implemented an ethernet stack in hardware with speed of 10/100 MBit. It uses a cycloneII device and a little board with phy of MTIP. 

 

The engineer told me, thats not easy to implement a stack faster than 100Mbit couse of the DMA controller and memory bandwidth. May be it is impossible to do that. 

 

Or my be a stratix device helps. I dont know. 

 

http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/ph34r.gif  

 

I have tried the NetwortAccelarationDesign but this is not what I need. Its to slow. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif
Altera_Forum
Honored Contributor II
136 Views

You should look at the Video over IP reference design mentioned in the above posting. That is a hardware implementation of RTP.

Altera_Forum
Honored Contributor II
136 Views

I&#39;m trying to quickly get a near-line rate udp sender/receiver going on a cyclone eval board (with 10/100 PHY). I started by basically merging the Video over IP reference design with the NetworkAccelerationDesign. I managed to get something running well enough to receive garbled UDP messages, but now I&#39;m stuck.  

 

Are the UDP/IP or 100/1000 PHY interface functions used in the Video Over IP ref design tested for use with a 10/100 PHY? The app note (AN374) doesn&#39;t provide much info on how to use the PHY interface function in 100 mode.  

 

For example, would all of my system clocks be 25MHz in this mode, instead of 125MHz? And would I leave the upper nibble of the Rx and Tx ports unconnected? Are there any other issues I should be careful of in this mode?  

 

Has anyone else tried to do this?  

 

Thanks! 

 

Tim
Altera_Forum
Honored Contributor II
136 Views

hi i want to hardware based tcp stack using vhdl in fpga .i am using arria 5 development board can any one suggest how to go about with dis project

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