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Exponentiation

Altera_Forum
Honored Contributor II
1,462 Views

People,I want to perform an exponentiation in base 10 but the exponent is a variable and this is causing an error in 10,638 at the compilation.I wonder if there is another way to do an exponentiation with the base 10 and exponent is a variable without this error occurs. 

Thanks.
0 Kudos
5 Replies
Altera_Forum
Honored Contributor II
80 Views

what are you refering to? HDL? C?  

 

Please post some code and more details on your problem.
Altera_Forum
Honored Contributor II
80 Views

Ok, my code is below.It's a program that converts a number in bcd code to binary code when "c" is 0 and converts from binary to bcd when "c" is 1.The problem is at the exponentiation of the first loop(ebd). 

 

Library ieee; 

USE ieee.std_logic_1164.all; 

USE ieee.numeric_std.all; 

---------------------------------------------------------------------------------------------------------- 

Entity conv_bcd_bin_bcd is 

Generic(nbitsin:natural:=8; 

nbitsout:natural:=12); 

Port(X:in unsigned(nbitsin downto 1); 

c:in std_logic; 

Y:out unsigned(nbitsout downto 1)); 

end entity conv_bcd_bin_bcd; 

---------------------------------------------------------------------------------------------------------- 

Architecture struc of conv_bcd_bin_bcd is 

Begin 

abc:Process(c,X) 

variable aux,cont:integer; 

Begin 

aux:=0; 

cont:=0; 

if c='0' then 

ebd:for i in 1 to (nbitsin/4) loop 

aux:=aux + (to_integer(X(4*i downto 4*i-3))*10**(cont)); 

if(to_integer(X(4*i downto 4*i-3))<10) then 

cont:=cont+1; 

else 

cont:=cont+2; 

end if; 

end loop ebd;  

Y<=to_unsigned(aux,nbitsout); 

else 

aux:=to_integer(X);  

rdf:for i in 1 to (nbitsout/4) loop 

Y(4*i downto 4*i-3)<=to_unsigned((aux mod 10),4); 

aux:=aux/10;  

end loop rdf; 

end if; 

end process abc; 

end architecture struc; 

 

Thanks.
Altera_Forum
Honored Contributor II
80 Views

bcd(8 bits) => binary, needs 

multiply MSB digit by 10 and add LSB digit 

 

binary(8 bits) => BCD  

divide by 100 then result is MSB digit, divide remainder by 10 the result is middle digit, last remainder is LSB digit 

 

Just off my head, needs verification
Altera_Forum
Honored Contributor II
80 Views

Are there another suggestions about it using the same code above?

Altera_Forum
Honored Contributor II
80 Views

Well your code sounds like software approach not VHDL. 

Your algorithm does not look right especially so the 10** 

You must first define a correct algorithm then implement it in HDL
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