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Altera_Forum
Honored Contributor I
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External SRAM instruction memory trouble

Hi, 

 

I have a program that seems to run in external SRAM. I am debugging using a hex display on a PIO port. I can write to the display, The timer interrupt service routine is executed. The main loop seems to be running.  

 

My problem is that there is no output from the JTAG UART. Typing on the console is echoed, (maybe the echo is local?), but alt_printf() produces no output. alt_printf() lines don't hang either.  

 

I have other configurations with internal SRAM that work fine on the same hardware. 

 

Where should I start debugging to fix this problem?  

 

Here is some stuff from system.h: 

# define ALT_MODULE_CLASS_jtag_uart_0 altera_avalon_jtag_uart# define JTAG_UART_0_BASE 0x81038# define JTAG_UART_0_IRQ 0# define JTAG_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0# define JTAG_UART_0_NAME "/dev/jtag_uart_0"# define JTAG_UART_0_READ_DEPTH 64# define JTAG_UART_0_READ_THRESHOLD 8# define JTAG_UART_0_SPAN 8# define JTAG_UART_0_TYPE "altera_avalon_jtag_uart"# define JTAG_UART_0_WRITE_DEPTH 64# define JTAG_UART_0_WRITE_THRESHOLD 8 

 

// The external SRAM is connected here 

# define ALT_MODULE_CLASS_generic_tristate_controller_0 altera_generic_tristate_controller# define GENERIC_TRISTATE_CONTROLLER_0_BASE 0x100000# define GENERIC_TRISTATE_CONTROLLER_0_IRQ -1# define GENERIC_TRISTATE_CONTROLLER_0_IRQ_INTERRUPT_CONTROLLER_ID -1# define GENERIC_TRISTATE_CONTROLLER_0_NAME "/dev/generic_tristate_controller_0"# define GENERIC_TRISTATE_CONTROLLER_0_SPAN 524288# define GENERIC_TRISTATE_CONTROLLER_0_SRAM_DATA_WIDTH 16# define GENERIC_TRISTATE_CONTROLLER_0_SRAM_MEMORY_SIZE 524288# define GENERIC_TRISTATE_CONTROLLER_0_SRAM_MEMORY_UNITS 1# define GENERIC_TRISTATE_CONTROLLER_0_TYPE "altera_generic_tristate_controller"
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Altera_Forum
Honored Contributor I
53 Views

Browse the forum. This is a FAQ. 

You'll find a lot of similar issues, and solutions. 

Anyway, first of all check if you selected jtag_uart_0 both in project properties (as stdout device) and in the Run/Debug configuration (for Nios II terminal communication).
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