Honored Contributor II
11-11-2014 09:12 PM
I have already posted about this issue, but for some reason the text in those posts are not visible.I am trying to implement an interface for external SRAM on Qsys. I am using a Generic Tri-State Controller connected to Tri-State Conduit Pin Sharer connected to Tri-State Conduit Bridge. I am quite new to FPGAs so this may not be the correct approach. I then tried to test the memory using the default memory test application in Nios. I received the error "-Data bus test failed at bit 0x1". In order to dig a little further I found that after writing "1" to the base address 0x00080000, reading that same address returns "1010101". When I try to signal tap the address and data lines I don't see any changes. I may have the wrong parameters for the Generic Tri-State controller, I could not find all the information I needed from the data sheet http://www.cypress.com/?docid=32763. I have attached the sopc info file. Please help. Thanks in advance.