I'm trying to implement something similar to the MMC interface with the Nios II through DMA and/or Avalon bus. This interface consists of 1 clock and 5 bi-directional data signals.In the SOPC builder, I've added an interface to user logic with those signals defined, then tried using avalon register slave, avalon memory slave, and avalon master through the bus interface type pull-down selection. However, all gave me some sort of errors messages. Please advise. Thanks.
Is the birdirection signals used in such a way that it can be used with the avalon user interface? (What I mean is it something like write, write, write, write, read ?)Now what we need are those error messenges http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif
For the bi-directional signals, I've selected them as inout as the direction and data as the type, since they will be transferring data.Here are the error messages. When set as Avalon Master, clock type is flush(?), bidir is data:
ERROR: slave avalonM is not mastered by anyone Error in processing. System NOT successfully generated.When set as Avalon Register Slave, clock type is irq, bidir is data:
ERROR: name (e_signal=HASH(0x36f8614)) is no good for a signal Error in processing. System NOT successfully generated.When set as Avalon Memory Slave, clock type is irq, bidir is data:
Error: Generator program for module 'cpu' did NOT run successfully. generator cmd was 'c:/quartus//bin/perl561/bin/perl -Ic:/altera/kits/nios2/bin/europa -Ic:/quartus/sopc_builder/bin -Ic:/quartus/sopc_builder/bin/europa -Ic:/quartus/sopc_builder/bin/perl_lib -I. -Ic:/altera/kits/nios2/components/altera_nios2 -Ic:/altera/kits/nios2/components/altera_nios_dev_board_stratix_1s10_es -Ic:/altera/kits/nios2/components/altera_nios_custom_instr_endian_converter -Ic:/altera/kits/nios2/components/amd_avalon_am29lv065d_flash -Ic:/altera/kits/nios2/components/altera_nios_dev_kit_stratix_edition_sram -Ic:/quartus/sopc_builder/components/altera_sopc_builder -Ic:/altera/kits/nios2/components/altera_nios_dev_board_stratix_1s40 -Ic:/altera/kits/nios2/components/altera_nios2 -Ic:/altera/kits/nios2/components/altera_avalon_spi -Ic:/altera/kits/nios2/components/altera_avalon_cfi_flash -Ic:/altera/kits/nios2/components/altera_avalon_dma -Ic:/quartus/sopc_builder/components/altera_ahb_avalon_bridge -Ic:/quartus/sopc_builder/components/altera_avalon_avalon_ahb_bridge -Ic:/quartus/sopc_builder/components/altera_avalon_tri_state_bridge -Ic:/altera/kits/nios2/components/OpenCores_Avalon_10_100_Ethernet_MAC -IC:/JSF/CPU/user_logic_ext_flash_if -Ic:/altera/kits/nios2/components/altera_avalon_lan91c111 -Ic:/altera/kits/nios2/components/altera_avalon_lcd_16207 -Ic:/altera/kits/nios2/components/altera_nios_dev_kit_stratix_edition_sram2 -Ic:/altera/kits/nios2/components/altera_nios_multiply -Ic:/altera/kits/nios2/components/altera_nios_dev_board_cyclone_1c20 -Ic:/altera/kits/nios2/components/altera_avalon_user_defined_interface -Ic:/altera/kits/nios2/components/altera_plugs_library -Ic:/altera/kits/nios2/components/altera_avalon_cs8900 -Ic:/altera/kits/nios2/components/altera_nios_dev_board_stratix_1s10 -Ic:/altera/kits/nios2/components/altera_avalon_jtag_uart -Ic:/altera/kits/nios2/components/altera_avalon_asmi -Ic:/altera/kits/nios2/components/altera_avalon_onchip_memory -Ic:/altera/kits/nios2/components/altera_avalon_onchip_memory2 -Ic:/altera/kits/nios2/components/altera_avalon_timer -Ic:/altera/kits/nios2/components/altera_nios_custom_instr_divide -Ic:/altera/kits/nios2/components/altera_avalon_new_sdram_controller -Ic:/altera/kits/nios2/components/altera_nios_custom_instr_bitswap -Ic:/altera/kits/nios2/components/altera_avalon_epcs_flash_controller -Ic:/altera/kits/nios2/components/altera_avalon_performance_counter -Ic:/altera/kits/nios2/components/altera_avalon_sysid -Ic:/altera/kits/nios2/components/altera_avalon_uart -Ic:/altera/kits/nios2/components/altera_nios_custom_instruction -IC:/JSF/CPU/user_logic_ext_sram_if -Ic:/altera/kits/nios2/components/altera_user_board_setup -Ic:/altera/kits/nios2/components/altera_avalon_pio c:/altera/kits/nios2/components/altera_nios2/cpu_core_select.pl --system_name=jsfcpu --target_module_name=cpu --system_directory=C:/JSF/CPU --sopc_directory=c:/quartus/sopc_builder --sopc_lib_path=C:/JSF/CPU+c:/altera/kits/nios2/components+c:/quartus/sopc_builder/components+c:/altera/kits/nios2/components --generate=1 --verbose=0 --software_only=0 --module_lib_dir=c:/altera/kits/nios2/components/altera_nios2 --sopc_quartus_dir=c:/quartus/ --projectname=jsfcpu.quartus ' Error in processing. System NOT successfully generated.
As long as the NIOS is in complete control you will not need to make it a master.So if you are simply reading and writing to this device from the NIOS then you want to use it as a slave. With that said the error messege for that one just means that a signal name doesn't follow the normal conventions used (I'm guess it's the underscore but don't quote me on that). Is "e_signal" you're own name? If so just change it to something like esignal or signalEn (depending on what it does). Like I said I don't know if that's the cause or not (because it creates signals like read_n for example by default). Try turning off the Import button, then click on generic port list then modify that to what you want.
Thanks for the advice, and I'll try your suggestions.I honestly don't know where e_signal came from, since I didn't assign it. I've unticked the import option on all the User Logic functions. One last question, how is the Avalon register Slave different from the Avalon memory Slave? Aside from the typical naming and implication, I didn't quite find the answers in the PDF documents.
I'm guessing the difference between register and memory mode would be if you took advantage of dynamic word sizes. I've never used the memery slave type before but can votch that the slave register type is really easy to use.
also had such a problemtry the following the interface will need at least write,read, chipselect and one address line, you can set write,read,address as shared, and you must not connect the chipselect signal. I think the avalon bridge needs the write,read and address signal.
If you use the default list it gives you and connect the ones you need you should be fine. Even if you come up with a good name for each signal, it's going to tack some extra stuff onto that anyway. The default list will give you port names like: nios_processor_read_n where nios_processor was the name of the core.Leaving extra ports (like read_n) disconnected is fine, but you should have those assigned to meet the avolon bus spec (it's a standard bus so you need to follow some form of a conviention). Any logic that feeds nothing gets synthesized out so don't worry about using up more LEs adding the whole port list and not using all of it.
Ok, I've kept the address, write, read, and chipselect lines with the former 3 as shared. However, when I try to add bidirectional ports, the check mark in the shared box can't be unselected when define as data. The signals that I need to have come out externally don't get generated when either data or export is selcted as type. The way around this is to split each bidirectional port to have its own input and output ports, so it seems. It doesn't matter if the User Logic is set as Register or Memory slave.
That's correct. Keep an eye one the timing diagrams for read and write while you interface to your hardware. Also be sure to use CS and the R/W enables (probably write will be the only one you need) to latch data going on so that you don't accidentally latch data that was not intended for your hardware.