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External controller accesses

Altera_Forum
Honored Contributor II
823 Views

Is it possible for an external processor to read\write data to internal memory of the gate array that is implemented outside of the SOPC system

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6 Replies
Altera_Forum
Honored Contributor II
125 Views

Sure it is possible! 

(What would be the purpose of a sopc system without interface towards the world outside?) 

You can interface memory outside sopc system (either internal to FPGA or external) in several ways. You generally need to export Avalon MM bus signals and provide the necessary glue logic to your memory. Alternatively you can use a tristate bus component which can be directly connected to a typical async ram.  

You can even use a PIO, but not if you need performance (you must manually drive pio pins to emulate memory control signals: rd,wr,addr... )
Altera_Forum
Honored Contributor II
125 Views

Cris72, 

Thanks for your reply, but I wasn't really clear. I am interested to know if a processor or micro controller external to the gate array could interface to a memory that is internal to the gate array (either inside or outside the SOPC system). I think from your answer you assumed I meant the other direction (processor inside the SOPC system and memory outside the SOPC system or gate array)
Altera_Forum
Honored Contributor II
125 Views

The answer is again YES. 

I myself have a design where I do this: I interface an external processor to memory instantiated inside the fpg and I can do it with an altsyncram component instantiated outside sopc system, but I can also access another memory inside sopc system.
Altera_Forum
Honored Contributor II
125 Views

Great I was hoping this was going to be true. I assume that I will need a custom component if I want to connect my micro controller external to my gate array to an internal memory to the SOPC. I assume that I need to use the regular bus interface signals for this component (read, write, chip select, data , address etc.) Is there any special considerations or signalling issues I have to keep in mind ? I tried to get some info on the timing interface of the "on-Chip memory" but there didn't seem any available.

Altera_Forum
Honored Contributor II
125 Views

Designing the interface is not that hard. 

You need to use a custom component to connect to sopc modules, but in most cases this could be a simple _hw.tcl file which exposes Avalon MM interface signals. I attached a sample.  

Inside sopc builder this is seen as an Avalon MM master and you can directly connect it to onchip ram or any other Av MM slave; while outside of sopc you may need to provide some extra glue logic to comply with your processor external port. 

This is straighforward if this is the only MM master inside sopc system; instead, if you have Nios or other masters on the Avalon bus, you must be aware of bus arbitration and manage the required signals.
Altera_Forum
Honored Contributor II
125 Views

http://www.altera.com/literature/hb/nios2/external_processor_if.pdf 

 

Maybe in this paper you can find your answer
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