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Altera_Forum
Honored Contributor I
750 Views

External interrupt not triggering software exception

I currently hav a push button connected up to my IRQ input on my Nios. When the button is asserted, I expect to see my program counter jump to my exceptions section in my assembly source code. When the button is asserted, I do not see this behavior. I have enabled both the ienable bit for the 0th interrupt, and the status bit PIE.  

 

Any ideas why my exception is not executing?
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4 Replies
Altera_Forum
Honored Contributor I
32 Views

Well, this is the fastest I have ever answered my own question.. haha. 

 

At first, I only enabled bit 0 in the ienable register. I was watching the status register while debugging and noticed that the PIE bit was already set to '1'. Because of this, I did not worry about writing to it to enable it. 

 

Turns out, even though that bit was already set to '1', it was not actually allowing exceptions to occur. I had to make sure I set those bits regardless of if they were already enabled before. Seems as if they are already set, it shouldn't matter but apparently it does. Very interesting. 

 

So, if your exceptions are not being handled, make sure you are performing the following instructions. 

 

movi r8, 1 

wrctl ienable, r8 

wrctl status, r8 

 

Thanks, 

Matt
Altera_Forum
Honored Contributor I
32 Views

I do however have one more question for anyone knowledgeable about IRQ's. My nios is communicating with an RTL component. This component is sending a one clock cycle "pulsed" interrupt to the Nios. Will the Nios recognize this IRQ during its instruction cycle? Both the Nios and the RTL component are operating synchronously on the same clock.

Altera_Forum
Honored Contributor I
32 Views

If your interrupt pulse is too short NIOS can miss it. The best practice is to set the IRQ high (in RTL), and then reset it in NIOS in the interrupt service routine. So your RTL will also need an avalon slave port to talk to NIOS's data master.

Altera_Forum
Honored Contributor I
32 Views

Nios supports level-interrupt type, which means that slave sending interrupt signals need to stay high until Nios acknowledges it by disabling it once entering ISR.

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