Re: F2H Avalon Bridge f2h_sdram0_data_waitrequest got stuck

Altera_Forum · ‎05-24-2018

Hi all,

I met a problem hope someone can help.

I am using f2h_sdram0 to access the SDRAM. After building HPS system, I got the hps.xml file in handoff folder, part of the code is:

So looks like I have initialized the F2SDRAM reset signals. But sometimes the f2h_sdram0_data_waitrequest signal will always be high voltage?

So which option in HPS settings can change or influence that? Or it's because of some u-boot related issues?

Thank you

Altera_Forum · ‎05-30-2018

Hi!

I think I'm exactly in the same situation. I use a DMA CONTROLLER to transfer data from the HPS DDR to the FPGA side by using the F2SDRAM0 port.

Set up works fine until I try to start the DMA. BUSY flag rise immediately in the DMA CONTROLLER indicating that transfer start but no data are move (length size counter never decrease). DMA is stuck...

Which device are you using?

I'm working on a Achille board with ARRIA10 SOC component with quartus 16.1

I read many thread about configuring UBOOT to enable the F2SDRAM bridge but it was for older device...

Sorry, i think it's not the kind of answer you were expecting but maybe with sharing experience, ligth will show up...

Regards

Altera_Forum · ‎07-24-2018

Hi guys,

I'm facing the same problem with a slightly different design.

I have a Cyclone V SX with fpga2sdram enabled. Firmware is loaded by linux in userland with the device tree overlay method.

My DMA accesses are fine but once in a while, the wait_request signal get stuck at '1' and I have to reset the board to get it back to a functional state.

I have seen that there are several threads here with no answer from Altera. Also I found this article : https://support.criticallink.com/redmine/projects/mityarm-5cs/wiki/important_note_about_fpgahps_sdram_bridge;

I'll be glad to know if the problem is on the die and/or if there are some tips/workaround to make it work.

Cheers

Altera_Forum · ‎07-24-2018

Hi!

The solution for me was to re-compile UBOOT with the new hps.xml file generated by quartus.

In this file, according to my design, the F2SDRAM port is enable, so the device at power up start with the good configuration.

UBOOT factory configuration that I was using on the Achille development kit, only enable the HPS to FPGA LW bridge.

Regards

Altera_Forum · ‎07-26-2018

Well, I found something functional so far.

First, I have deactivated the fpga2sdram bridge in the device tree loaded with linux.

        fpgabridge1: fpgabridge@0xffc25080 {
            compatible = "altr,socfpga-fpga2sdram-bridge";
            reg = <0xffc25080 0x4>;
            bridge-enable = <0>;
        };

Then once in userland :

1- I force the fpga2sdram driver to unbind

echo -n "ffc25080.fpgabridge" > /sys/devices/platform/soc/ffc25080.fpgabridge/subsystem/drivers/altera_fpga2sdram_bridge/unbind

2- I load the FPGA with the device tree overlay method.

In the overlay, there is a fragment to enable the fpga2sdram bridge

        fragment@1 { 
            target = <&fpgabridge1>;
            __overlay__ { 
                bridge-enable = <1>;
            };
        };

3- I rebind the fpga2sdram driver

echo -n "ffc25080.fpgabridge" > /sys/devices/platform/soc/ffc25080.fpgabridge/subsystem/drivers/altera_fpga2sdram_bridge/bind

With this, I haven't see any issues anymore. I just hope it will last.