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F2H_SDRAM "WAITREQUEST" doesn't return to '0'

Altera_Forum
Honored Contributor II
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Hello, 

 

I'm using the Cyclone V SOC with a 128 bit F2H_SDRAM bus. 

Notes:  

 

1. I had to build a new pre-loader to make this bus work. 

2. My design doesn't communicate with the F2H directly - instead I use an Avalon Clock Crossing Bridge. 

 

Most of the time - everything functions correctly and I transfer data successfully to the HPS's SDRAM. 

However, once I increase the amount of written data over a certain amount - the "WAITREQUEST" signal of the Avalon Clock Crossing Bridge goes high (as observed with Signal-Tap) and never returns back to '0'. 

 

What can be the cause ?
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