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FIFOed Avalon Uart

Altera_Forum
Honored Contributor II
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I have posted the FIFOed avalon UART in the Hardware Projects area. It is the standard UART that comes with Nios but it has additional features such as FIFOs and hardware CTS  

 

fifoed avalon uart project (http://www.niosforum.com/pages/project_details.php?p_id=89&t_id=18)
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Altera_Forum
Honored Contributor II
550 Views

I longshot. 

I read thie part of forum and i'm really curious about your UART+FIFO block. 

Can you send me that please? 

My email: tonnoplast@tiscalinet.it 

 

Well...i should send an array through UART RS232 but even if it seems ok the creation of the same array and creation file for UART...it seems doesn't send anything, or better, leds light switch on and off (and if i well remember it's a behaviour of a UART on function) but if i try to read bytes sended (By SerialVisa program) , nothing arrive and Visa time outs. 

Have you some suggests? 

Thank you
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Altera_Forum
Honored Contributor II
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Hi...file in this link it&#39;s 0 kbytes...not good i think http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif

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Altera_Forum
Honored Contributor II
550 Views

FIFOed Avalon Uart Project 

 

..this file i&#39;m referred to..Doesn&#39;t work
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Altera_Forum
Honored Contributor II
550 Views

As a beginner to the world of Nios I&#39;m wondering how this component (enhancement to the Altera UART) has been developed. 

I read chapter 10 "Developing Components for SOPC Builder" found in the Quartus II Handbook which shows how to develop custom peripherals based on HDL files. When looking into the attached ZIP file, all I can find are some C and Perl files. 

Was this component developed in VHDL and exported to Perl or were all of the enhancements directly added into the Perl script? Can anybody point me to literature that describes how I can enhance an arbitrary component originally created by Altera? 

 

Thanks, 

Markus
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Altera_Forum
Honored Contributor II
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Has a new revision of FIFOed been released lately ? Any additional bug fixes ?  

Also is there any way that I could add additional data as a seperate entry to the FIFO i.e. on receiving serial data for each byte\word written into the FIFO is there anyway that I could attach\write a Time Tag to be stored into the FIFO for each entry ? 

 

If this is going to be too hard\impossible - then how can I use the standard SOPC UART with an external\internal FIFO that I can write TTAG values to for each serial massage stored in the FIFO ? 

 

Thank you in advanced 

 

Shmuel
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Altera_Forum
Honored Contributor II
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Hello, 

 

I&#39;m having a problem in the compilation when the RX FIFO depth and TX FIFO depth are different. 

 

It seems that there is a bug when generating the VHDL code: 

 

If TX FIFO depth is 8 bytes and RX FIFO depth is 16 bytes: 

Error (10344): VHDL expression error at slot1_uart.vhd(1562): expression has 4 elements, but must have 3 elements 

 

If TX FIFO depth is 8 bytes and RX FIFO depth is 32 bytes: 

Error (10344): VHDL expression error at slot1_uart.vhd(1562): expression has 5 elements, but must have 3 elements 

 

And so on.. 

 

 

If the two depths are the same, no error occurs. 

 

Is there anyone experiencing the same problem? 

 

Thank you.
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Altera_Forum
Honored Contributor II
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Looks like it is a problem in the hw.tcl file  

 

I will post a new hw tcl file. give it a try.  

Long shot
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Altera_Forum
Honored Contributor II
550 Views

Dear Long shot, 

Please could you let me know when you make the fix and if it works ? 

Also is there any way for me to attach\insert additional external data to the Serial Data stored in the FIFO e.g. a Time Tag ? 

How well does the FIFOed work - how well ahs it been tested ? 

 

Thanks in advanced 

 

Shmuel
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Altera_Forum
Honored Contributor II
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I just tried to use the FIFOed UART for the first time and have had difficulties. I am using Quartus 8.1 so I used version 7.1 of the FIFOed UART. I have 3 instances of the UART in my design. When I compile the design I get the following errors: 

 

 

system_description/alt_sys_init.c:83: error: `UART_RS232_FREQ&#39; undeclared here (not in a function) 

 

system_description/alt_sys_init.c:83: error: initializer element is not constant 

 

system_description/alt_sys_init.c:83: error: (near initialization for `uart_rs232.freq&#39;) 

 

system_description/alt_sys_init.c:84: error: `UART_EMM_FREQ&#39; undeclared here (not in a function) 

 

system_description/alt_sys_init.c:84: error: initializer element is not constant 

 

system_description/alt_sys_init.c:84: error: (near initialization for `uart_emm.freq&#39;) 

 

system_description/alt_sys_init.c:85: error: `UART_ISO_SCI_FREQ&#39; undeclared here (not in a function) 

 

system_description/alt_sys_init.c:85: error: initializer element is not constant 

 

system_description/alt_sys_init.c:85: error: (near initialization for `uart_iso_sci.freq&#39;) 

 

make[1]: *** [obj/alt_sys_init.o] Error 1 

 

make: *** [system_project] Error 2 

 

 

I have talked to my FAE who says that lots of customers have had success using this UART. He sent me his copy of the source files which all match the files from the forum. 

 

In the system.h file it appears that there isn&#39;t a clock associated with the FIFOed UART which may be part of the problem. Is anyone else running into issues like this?
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Altera_Forum
Honored Contributor II
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Hi, 

great stuff. 

One question, are you just wrapping the original avalon uart, or have you programmed it from the scratch? 

We need to be able to change parity at run time, which is not possible with the standard avalon uart. 

 

Would you consider including that if possible? 

 

Apus
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Altera_Forum
Honored Contributor II
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Yes, any code for being able to change the parity bit or stop bits setting in software would be great! I'm surprised that Altera didn't do this themselves in their UART, but clearly not. Sigh. 

 

Simon
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Altera_Forum
Honored Contributor II
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We just mapped the opencore uart into the avalon system. Works fine. 

But it's pretty useless not to be able to change parity at runtime. 

 

apus
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Altera_Forum
Honored Contributor II
550 Views

Hi again, 

I've just tried to use this with version 8.1 and have come across a minor problem, hinted at in the documentation, which is that it can't get the right clock in the SOPC GUI, but I fixed that by editting the .tcl file to hard code the clock to 100MHz (ok for me, but not for general use!). 

 

I've just tried to build my project (VHDL) and it complained that the USEDW was the wrong size - should be 4 but was 9 bits - on the RX fifo. I created the component with 512 bytes of FIFO, so 9 bits is correct, but the component declaration at the head of the VHDL file hard sets the usedw width to (in this case) 3 downto 0. 

 

Just spotted the gotcha in me fixing it by setting it to 8 downto 0 which is that the TX fifo uses 16 bytes, and so is 3 downto 0, so that's now complained. 

 

So I've changed that to use lpm_width generic, but that's now complained elsewhere. It would appear that lpm_width is set to 8 on my TX fifo, despite only having 16 bytes..... 

 

Is this all because I'm using 8.1, not 9.0? 

 

Cheers, 

Simon
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Altera_Forum
Honored Contributor II
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Ok, I've just set TX and RX depths to be the same, and that seems happy. Now the BSP isn't compiling properly because in the IOCTL routines it uses dev which is undefined (lines 701 and 740). I've just looked at the altera driver and that uses sp in those places, so have changed to that.... 

 

It would also appear that various# define's didn't make it into system.h, namely 

RS422_UART_PARITY, RS422_UART_STOP_BITS, RS422_UART_BAUD, RS422_UART_DATA_BITS, RS422_UART_FREQ 

Not at all sure why. 

 

And a minor thing, in SOPC Builder when I click Generate it asks me if I want to save, so I say Yes, but when it has finished generating and I exit SOPC builder it asks me again if I want to save even though I've not changed anything. 

 

Again, is this all because I'm using 8.1, not 9.0? 

 

Cheers, 

Simon
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Altera_Forum
Honored Contributor II
550 Views

Next 'bug'. In alt_sys_init.c when it tries to create the component the compiler complains that FIFOED_avalon_uart_ioctl_fd is undefined anywhere, so the# define on line 91 of fifoed_avalon_uart_fd.h needs to be changed to have a lower case "FIFOED" in the definition, as that is what is in the .c file. 

 

Excellent - now my BSP builds. Slight concern with the missing things in system.h because they'll need setting each time I run SOPC Builder...... sigh. 

 

Let's see if I can get the FPGA to build now.... 

 

Cheers, 

Simon
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Altera_Forum
Honored Contributor II
550 Views

In 9.0.1 version of fifoed_avalon_uart, IRQ threshold logic is broke - can cause an interrupt to go away without user handling, which in turn can cause a lockup in the altera_irq_handler (which expects an IRQ, once asserted, to never to go away without a SW action).  

 

Problem is that USED outputs on the internal FIFOs wrap around when FIFO is full. E.g. lets say you use FIFO depths of 128 and TX IRQ threshold of 1 and keep on sending data to the FIFO, the TXREADY interrupt will be de-asserted when FIFO has at least 1 entry but will be re-asserted when FIFO is full (because USED on TX FIFO will transition from 0x7F to 0); at that point IRQ handler will be called. While in the handler, the FIFO will get drained at least one character, USED will transition 0->0x7F and IRQ will be deasserted.  

 

Proper fix is to either use wider USED field on the FIFO (WIDTHU=log2(DEPTH)+1) or to consider FULL flag while looking at USED to determine TXREADY/RXREADY status for generating the interrupt. 

 

Here is the fix to mk_em_uart.pm:  

 

1869c1869,1870 

< ([e_signal->new ({name => "tx_almost_empty", never_export => 1}), "tx_used <=$Options->{tx_IRQ_Threshold}" ] )if $Options->{use_tx_fifo}; 

--- 

> ([e_signal->new ({name => "tx_almost_empty", never_export => 1}), "(tx_used <=$Options->{tx_IRQ_Threshold}) && tx_not_full" ] )if $Options->{use_tx_fifo}; 

>  

1995c1996 

< ([e_signal->new ({name => "rx_at_threshold", never_export => 1}), "(rx_used >=$Options->{rx_IRQ_Threshold}) || timer_timout" ] )if $Options->{use_rx_fifo}; 

--- 

> ([e_signal->new ({name => "rx_at_threshold", never_export => 1}), "(rx_used >=$Options->{rx_IRQ_Threshold}) || rx_full || timer_timout" ] )if $Options->{use_rx_fifo};
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Altera_Forum
Honored Contributor II
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Hi 

 

Has some one used the EOP for the FIFOed uart. I want to use the dma to trasfer data to ram. 

I had it working with the altera uart, but with the fifoed uart the dma never stop due to the eop char. 

 

Christo
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Altera_Forum
Honored Contributor II
550 Views

Hi 

this fifoed uart is really great it solved me a lot of problems!! 

Now I have a question. 

I defined:# define UART_RX_FIFO_USED(base) IORD(base, 6)# define UART_TX_FIFO_USED(base) IORD(base, 7) 

To get the number of chars in the tx and rx FIFO, but when I call: 

printf("\nBytes in fifo RX:%i TX:%i", UART_RX_FIFO_USED(FIFOED_AVALON_UART_0_BASE), UART_TX_FIFO_USED(FIFOED_AVALON_UART_0_BASE)); 

I always get 0. 

 

And this is what I have in system.h: 

[…] 

/* 

* fifoed_avalon_uart_0 configuration 

*/# define ALT_MODULE_CLASS_fifoed_avalon_uart_0 fifoed_avalon_uart# define FIFOED_AVALON_UART_0_BASE 0x4820a0# define FIFOED_AVALON_UART_0_FIXED_BAUD 0# define FIFOED_AVALON_UART_0_IRQ 4# define FIFOED_AVALON_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0# define FIFOED_AVALON_UART_0_NAME "/dev/fifoed_avalon_uart_0"# define FIFOED_AVALON_UART_0_SPAN 32# define FIFOED_AVALON_UART_0_TYPE "fifoed_avalon_uart"# define FIFOED_AVALON_UART_0_USE_CTS_RTS 0 

[…] 

 

What am I doing wrong? 

Thanks 

 

(Pleas tell me if it is the wrong place to ask this)
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Altera_Forum
Honored Contributor II
550 Views

Hi 

 

Possible bug in FIFOed uart9.3 

 

I am routing 9 Uarts to 1 all running at 460800baud. I had to implement RTS for each in the FPGA using the exported fifo registers - would be a nice standard feature:). All worked great in buffering the rx-ed data, but I started loosing rx data as soon as I started sending data back on the uarts. 

 

It turned out that I lost all the data in the rx buffer (on the drivers side - not fifo) due to a rx interupt that were generated as soon as I tx any data when the rx buffer is full (rx buffer wrapped to start). I have for now solved the problem by clearing the rx irq when the rx buffer is full without reading the reg. Not nice but it is working for now 

 

Another possible bug is in the UART status reg (fifoed_avalon_uart_reg.h) is the position of the last two registers, FIFOED_AVALON_UART_STATUS_RX_TH_MSK (13) and FIFOED_AVALON_UART_STATUS_GAP_MSK (14). In the VHDL code they are swapped when the are passed to the status_reg. 

 

I am using NIOS/Quartus ver 10 on Win7 64bit PC so the IRQ buffer problem might be as a result of this.  

 

Thanks for a great UART component! 

Herman
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Altera_Forum
Honored Contributor II
567 Views

I am interested in the FIFOed. I have two questions:- 

1. Is there any way that the size of FIFOs can be increased ? 

2. Can the FIFOed be connected to the standard Altera DMA Core so that the DMA can be used to trandfer data to\from the UART ? 

 

Thanks in advanced
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Altera_Forum
Honored Contributor II
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If you need dma, you really want a uart that has a descriptor based interface - more like that seen on ethernet chips. 

A software solution might be to put down a 2nd nios with minimal, tightly coupled code+data to act (effectively) as a progammable dma engine.
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