Hi.I have just purchased an evaluation board containing an Altera Cyclone (EP1C12Q240C6). (It's the dirt-cheap one from FutureElectronics.com) I have blundered around with Quartus II 4.1 and the Nios II IDE 1.0. I am using the NIOS II in evaluation mode, so I understand that I have a time limit. I managed to get a tutorial system running, but only while the JTAG connector is connected. After I hit reset on the board, or I disconnect the JTAG connector, the board reverts back to a default system that came pre-programmed with the board. My guess was that this is some limitation with the "tethered" OpenCore stuff so I tried to set it to "untethered" by going into Quartus II v 4.1, Assignment Menu Settings option Compilation Process dialog I checked (selected) "Disable OpenCore Plus hardware evaluation feature", hoping that it would program the FPGA with the time-limited version of the core ("Untethered"). After doing this, I managed to disconnect the JTAG cable and keep the system running. However, as soon as I hit Reset, the programming is lost and the FPGA reverts back to the factory default system. My question (at last) : Is there any way for me to clobber the factory default system and actually program the FPGA in some sort of permanent way (so that it starts up in the latest system that I have programmed into it?) Doing my best... Thanks.
Read it...The FPGA's we used in university were one-shot devices: you burned them and that was it. The guys at the office just told me that newer, reprogrammable FPGAs load their configurations from a flash memory. I guess I was overriding the configuration via JTAG, but not overwriting the configuration flash memory. Thanks for the tip, though... without it I wouldn't have asked any questions at the office. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/biggrin.gif