Nios® II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
12435 Discussions

FPGA image in flash/boot copier

Altera_Forum
Honored Contributor II
873 Views

What should the offset be for the FPGA image in CFI flash be if I'm also programming software to flash? I'm seeing conflicting info online and would just like someone to explicitly say what the offset should be. Thanks!

0 Kudos
4 Replies
Altera_Forum
Honored Contributor II
98 Views

It's design dependent. There is no fixed value. Are you looking for the offset for a particular board? If so, please let us know which board.

Altera_Forum
Honored Contributor II
98 Views

I guess so. I did not realize it was board dependent. The board is a Cyclone III starter board. Thanks for the help.

Altera_Forum
Honored Contributor II
98 Views

I finally got this project to work. The offset for the image on the starter board is 0x0020000. By programming the flash using a .pof file in programmer, and then using the FlashProgrammer in the NIOS SBT to program the .elf and start the processor, the thing works. For some reason I can't get it to work with just the flash programmer or the Quartus programmer alone.  

 

The Quartus programmer seems to leave the processor paused at reset, and manually resetting it with the button doesn't seem to have any effect unless the processor is already running. If just the NIOS SBT flash programmer is used, the FPGA is not reconfigured on power up. At least it works. 

 

Note: I didn't find this info anywhere online until today, but if you have the NIOS programs saved in ROM somewhere to be loaded at boot (and not initialized to on-chip memory with a .hex file) the memory where the .text section is being run from must also be connected to the NIOS data master and not just the instruction master. I couldn't figure out why my program would work if I omitted the flash and just ran from on-chip memory, but did not work when I tried to boot it from flash. Evidently the boot copier will use the data bus to copy the needed files into RAM to be run.  

 

Just thought I'd post that in case anyone ran into the same issue somewhere.
Altera_Forum
Honored Contributor II
98 Views

Both the 'flash' boot code and the JTAG download work by running code on the nios cpu (from a block of internal memory) that writes copies the data into the required instruction space. 

 

However, even if you aren't using the nios cpu to load the code, you may need data access to the instruction memory. 

 

The program '.text' section probably contains readonly data - look at the symbol table and/or request the linker generate a map file. 

 

The other fubar is the jump tables used for C switch statements, with gcc4 (as built by Altera) these are forced into the .code section - and there is nothing you can to do change this without rebuilding the compiler.
Reply