Nios® V/II Embedded Design Suite (EDS)
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FPGA manager core in hps

Altera_Forum
Honored Contributor II
‎11-22-2015 11:30 AM
1,132 Views

I read one of the thing for fpga core that purpose to control the fgpa from hps. is this core power up default had been enabled to be used?

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Altera_Forum
Honored Contributor II
‎11-23-2015 01:09 PM
367 Views

this the feature come with the hps that ready to be used. what application that you plan to design on this anyway?

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