FPGA startup - all I/O go to 1 for 0.5 seconds...?

Altera_Forum · ‎02-22-2006

Hi all,

I am using NIOS-II Cyclone 2C35 evalution kit from Altera for project development.

The problem is that after every power-up of the system the FPGA during reconfiguration sets all the I/O ports to logic 1, for approx. 500ms after power-up, 250ms if only reconfigured.

This can cause serious troubles in my application, since certain outputs can only be switched on in specific situations for short time (due to the nature of the system controlled). Does anyone have an idea how to bypass this problem? Is this correct behaviour of FPGA?

Thanks.

Altera_Forum · ‎02-22-2006

yes, it is correct for most FPGA. the io pins will have weak pull-high before config done.

You can add pull low resistor on the pin where you want it stay low.