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Altera_Forum
Honored Contributor I
1,812 Views

FPGA-to-HPS Bridges Design Example

Hi Everyone, 

 

I'm working to develop an FPGA-HPS design which allows the FPGA to write to the HPS DDR3 and then have the HPS read from that memory space. So far this is the only example I've found for this type of design: https://www.altera.com/support/support-resources/design-examples/soc/fpga-to-hps-bridges-design-exam... I was able to modify the Quartus project for my DE0-Nano-SoC Cyclone V board, but when trying to compile the baremetal application in DS5 EDS Eclipse I ran into this error: (Path)/Altera-SoCFPGA-HardwareLib-FPGA2HPS-Bridge-CV-GNU/alt_bridge_manager.c:93: undefined reference to `memcpy_s'. Now all the files including this alt_bridge_manager.c came directly from the Altera design example. So far I've tried changing the std in the makefile from C99 to C11, no luck. Also, I found a post stating that if you put: #define __STDC_WANT_LIB_EXT1__ 1  

Then it would fix the error, however that did not work either, and I found that when running build in the DS5-Workspace in eclipse it actually stripped that line out of the file. I'm pretty lost here and would appreciate any help on the project for additional info: 

 

Board: DE0-NANO-SoC Cyclone V 5CSEMA4U23C6 

OS: Windows 10 

IDE: Eclipse DS5 Workspace started from SoC EDS Terminal 

Project: https://www.altera.com/support/support-resources/design-examples/soc/fpga-to-hps-bridges-design-exam... 

 

EDIT: Ran the make from the SoC EDS, no longer strips out that# define statement like the DS5 Eclipse does, but still throws the error
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4 Replies
Altera_Forum
Honored Contributor I
239 Views

Can confirm the behavior. Compiles correctly with 16.0 but fails with 18.0. 

 

That file does not come with the design example, it is copied into the directory by Eclipse from embedded/ip/hps/altera_hps/hwlib/src/hwmgr/soc_cv_av/alt_bridge_manager.c. 

 

The crux of the issue is that, between 16.0 and 18.0, someone changed that file and replaced three calls to memcpy with calls to a C11 function memcpy_s (which does the same thing as memcpy, except it also checks for destination buffer length). 

 

However, the cross-compiler that comes with 18.0 (Sourcery CodeBench 6.2.0) does not have an implementation of memcpy_s. 

 

To build it with 18.0, you either need to replace memcpy_s with memcpy directly in the original inside the EDS tree (don't forget to remove the extra argument), or edit the makefile. 

To HWLIBS_SRC, add 

 

memcpy_s.c mem_primitives_lib.c safe_mem_constraint.c ignore_handler_s.c  

To CFLAGS, add  

 

-I$(HWLIBS_ROOT)/src/safeclib -I$(HWLIBS_ROOT)/include/safeclib  

To ALL_HWLIBS_SRC, add  

 

$(wildcard $(HWLIBS_ROOT)/src/safeclib/*.c)
Altera_Forum
Honored Contributor I
239 Views

 

--- Quote Start ---  

Can confirm the behavior. Compiles correctly with 16.0 but fails with 18.0. 

 

That file does not come with the design example, it is copied into the directory by Eclipse from embedded/ip/hps/altera_hps/hwlib/src/hwmgr/soc_cv_av/alt_bridge_manager.c. 

 

The crux of the issue is that, between 16.0 and 18.0, someone changed that file and replaced three calls to memcpy with calls to a C11 function memcpy_s (which does the same thing as memcpy, except it also checks for destination buffer length). 

 

However, the cross-compiler that comes with 18.0 (Sourcery CodeBench 6.2.0) does not have an implementation of memcpy_s. 

 

To build it with 18.0, you either need to replace memcpy_s with memcpy directly in the original inside the EDS tree (don't forget to remove the extra argument), or edit the makefile. 

To HWLIBS_SRC, add 

 

memcpy_s.c mem_primitives_lib.c safe_mem_constraint.c ignore_handler_s.c  

To CFLAGS, add  

 

-I$(HWLIBS_ROOT)/src/safeclib -I$(HWLIBS_ROOT)/include/safeclib  

To ALL_HWLIBS_SRC, add  

 

$(wildcard $(HWLIBS_ROOT)/src/safeclib/*.c) 

--- Quote End ---  

 

 

Thanks eugenek! Seems like you're helping me all over the forum. I was able to get the project to compile, but now I'm not sure how to get it to run on the board. The instructions that came with the example only say "Run the project from eclipse" but I tried hitting running either of the .axf files generated (the uboot or the example_design) and both gave eclipse errors about failing to start process. Am I supposed to copy these to the board then restart the board? I'm sorry I've never run a baremetal app before.
Altera_Forum
Honored Contributor I
239 Views

I just happen to be studying the same area. I haven't tried baremetal apps either, but it looks like you have to go to Run -> Debug Configurations -> DS-5 Debugger -> FPGA2HPS-Bridge and set things up there. Check out https://www.altera.com/documentation/lro1424280108409.html .

spere34
Beginner
239 Views

Hey,

I edited the make file as you have mentioned above. But I couldn't build it . It has ended with following error.

 

make: *** [Makefile:98: cycloneV_hps_arm_a9_0.h] Error 1   Altera-SoCFPGA-HardwareLib-FPGA2HPS-Bridge-CV-GNU         C/C++ Problem

Could you please help me for this error.

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