Nios® II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
12408 Discussions

FPGA-to-HPS Bridges Design Example

Altera_Forum
Honored Contributor I
1,639 Views

I am looking at the FPGA-to-HPS Bridges Design Example in Altera website, https://www.altera.com/support/support-resources/design-examples/soc/fpga-to-hps-bridges-design-exam.... I downloaded the project for Cyclone V SoC, and opened the hps_system.qsys, there is a component, AXI Cache Secruity Bridge, I can not find document for this bridge, anyone know what it is for? Thanks......

0 Kudos
1 Reply
Altera_Forum
Honored Contributor I
385 Views

Hi, 

 

It is a custom IP, you can see the Verilog code given in directory "CV_FPGA_to_HPS_Bridge_Design_Example\ip\axi_cache_secruity_bridge". 

For more information read the commented lines in .v file and link below. 

https://www.altera.com/support/support-resources/knowledge-base/embedded/2017/how-do-i-configure-my-... 

 

Best Regards, 

Anand Raj Shankar 

(This message was posted on behalf of Intel Corporation)
Reply