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Altera_Forum
Honored Contributor I
1,180 Views

FPGA to SDRAM AXI Transfer

Hello, 

 

I'm doing a project with Arria V SoC using the HPS and FPGA parts. In the FPGA, I have a custom IP with AXI Master interface on it. 

This IP should read and write from/to the SDRAM directly. However, I can only do read operation! The write operation does not work. 

The data in SDRAM is provided by HPS (running Linux). For now, I'm using /dev/mem to write the data to the SDRAM. 

Using the same method, I found that the data is never written from FPGA. 

1. Can you help me with this issue? Anyone has already done a work using AXI and SDRAM? 

2. In Qsys, my AXI master should be connected to the SDRAM, right? Did I do some mistake? I connect it to f2h_sdram0_data, not f2h_axi_slave on hps_0. 

3. Is there any configuration that I need to do in the AXI to perform read and write? 

 

Thank you so much for your help.
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4 Replies
Altera_Forum
Honored Contributor I
74 Views

Never mind. Found it. 

 

 

--- Quote Start ---  

Hello, 

 

I'm doing a project with Arria V SoC using the HPS and FPGA parts. In the FPGA, I have a custom IP with AXI Master interface on it. 

This IP should read and write from/to the SDRAM directly. However, I can only do read operation! The write operation does not work. 

The data in SDRAM is provided by HPS (running Linux). For now, I'm using /dev/mem to write the data to the SDRAM. 

Using the same method, I found that the data is never written from FPGA. 

1. Can you help me with this issue? Anyone has already done a work using AXI and SDRAM? 

2. In Qsys, my AXI master should be connected to the SDRAM, right? Did I do some mistake? I connect it to f2h_sdram0_data, not f2h_axi_slave on hps_0. 

3. Is there any configuration that I need to do in the AXI to perform read and write? 

 

Thank you so much for your help. 

--- Quote End ---  

Altera_Forum
Honored Contributor I
74 Views

 

--- Quote Start ---  

Never mind. Found it. 

--- Quote End ---  

 

 

If you post your solution it can help others in the future, who will most likely be very grateful!
Altera_Forum
Honored Contributor I
74 Views

Hi, 

 

Perhaps you can refer to the following design example on using the FPGA to HPS SDRAM bridge: 

https://rocketboards.org/foswiki/projects/cyclevsocsdramperformanceexampledesign 

 

Regards, 

ccthum 

(This message was posted on behalf of Intel Corporation)
MSene1
Beginner
74 Views

Hi,

 

I am reopenning this issue because I am having the same problem.

Only my read interface is working but the write doesn't work.

If someone knows the solution I would be thankful.

 

thank you for your help

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