Hello everyone,Sorry about my poor english, i've developped a FPGA board which has a SST39VF6401B (Microchip flash), i'm using SOPC to configure the FPGA. I use Nios II to program flash (only blink leds) but when program flash, the only error is "no cfi table found". I also run program on the SD RAM to make sure my FPGA, RAM and JTAG still fine. Can anyone solve this problem or any suggestions? Thank you very much and best regards
Probably Altera HAL driver doesn't support your flash memory.AFAIK support is provided for Intel, AMD and Spansion flash chips. In this case I think you'd only need a minor change in the driver in order to identify SST39VF6401B chip and properly access its CFI table.
Hello Cris72,Thank you for replying me, i'm newbie. I also change into S29AL032D flash, and change some schematics (pull-up resistor 4k7 to pin WP# and BYTE#) to be suitable older design (using 16 bit data), but I have the same error ("no cfi table found"), i'm using FPGA EP3C25 (Cyclone III). Could you tell me how to change in the driver? or solve the second problem? Thanks very much
In such situations I'd try to manually access the flash device with IORD/IOWR and check if the hw interface is working as expected.Read the flash datasheet: a few IOWR and IORD are used to get basic flash information, like vendor and product Id and this is enough to exclude major errors in design.
Dear Cris72,Thanks for your advices but my situation is that i can't program flash via JTAG ("No CFI table found"), i also use S29AL032D flash with 16 bit data, its has the same problem. I wonder that there are something different in SOPC between Cyclone III and Cyclone II or between S29AL032D 8 bit data and 16 bit data. I have built a project for DE2 kit, it's worked fine in programming flash (S29AL032D 8 bit data). Do you have any ideas?
Does Nios reset vector point to flash?Please also check if the problem is only with Nios boot. I mean, check if fpga gets correctly configured after you press reset button. Do you use the same flash memory for configuration and Nios program?
Hello Cris72,Thanks for your reply. I configure reset vector to cfi_flash offset 0x00 and exception vector to sdram offset 0x20 (working with S29AL032D 16 bit data). I'm using EPCS16 for configuration and Nios program on Flash. My SDRAM and Flash are shared data (16 bit) and address. I can use debug->run as nios hardware to check SDRAM; it's run fine but when i program to flash, the program cannot run. Please help me!
I believe you have some problem with the bootloader.I guess you are using the standard bootloader provided by Altera; then you should have a boot_loader_cfi.srec file referenced somewhere in your project. Also check the Advanced.Hal.Linker parameters in BSP.
Hi Cris72,I'm using Nios II IDE, and Nios Programmer to program the Flash. When i configure the flash with on-chip memory. The software work fine but when i change it to SDRam (share 16 bit data and address with Flash), it can't worked! Is there any declaration or add something on hardware that i'm missing? or is there problem on shared bus? Please help me!
--- Quote Start --- If it works with onchip ram, there's definitely a problem with sdram configuration or with shared bus. --- Quote End --- Hi Cris72, Thanks for your reply, I'm working on the project with Judau and config for this project. About hardware: + I'm using the sdram 8Mbyte of Micron and using sdram controller core and check in (Share pins via tristate bridge, Tristate bridge selection i had chossed the tri_state_bridge which handle the cfi_flash). About timing of sdram controller i setting default. + I'm using the cfi_flash S29AL032D of Spainsion and using the CFI controller core. Address width is 21, Data width is 16 because cfi_flash sharing data and address with sdram (limited i/o pin in hardware). About the timing 40-160-40ns. And in the schematic WP#, RY/BY# pull up 4k7 resitor to 3V3, and pin 47 BYTE# (F_MODE) control by FPGA (assign F_MODE = 1'b1;) And i had made on chip ram 24KB for testing. The reset_vector using cfi_flash. The exception_vector using sdram. The nios ii config .text, .rodata, .rwdata, heap and stack i setting at sdram. My problem now is when i set .text, .rodata, .rwdata, heap and stack i setting at on chip ram and programing to cfi_flash complete after reset the LED test blink ok but when i set .text, .rodata, .rwdata, heap and stack i setting at sdram, the nios not working. Can you help me! Thanks and Regard!. Q.Cuong.