I'm working on Terasic ADC-SoC board that hosts a Cyclone V SoC device. I started the Quartus project by Golden Reference System Design (GRSD), given by Terasic. The GRSD is composed only by the SoC structure, wrote in verilog and it is fully compilated by Quartus Prime 17.0 Standard Edition. Then I changed the project name and created a bdf as top-level entity (project and the bdf files have obviously the same name), where I placed the soc system block diagram generated by Qsys and the pin connections. When I compile the project, Quartus gives the following error during the fitter execution: Error (179000): Design requires 154 user-specified I/O pins -- too many to fit in the 145 user I/O pin locations available in the selected device Info (179001): Current design requires 154 user-specified I/O pins -- 154 normal user-specified I/O pins and 0 programming pins that have been constrained to use dual-purpose I/O pin locations Info (179002): Targeted device has 145 I/O pin locations available for user I/O -- 117 general-purpose I/O pins and 28 dual-purpose I/O pins I didn’t find a lot about this issue, except this file https://www.altera.com/documentation/hco1406563361926.html . It is suggested to update Quartus at the 17.1 version where the problem has been fixed. I did it but the problem persists. I also found this post http://www.alteraforum.com/forum/showthread.php?t=29620 and I checked the pin planner and the assignments, but it is all right. Indeed, both pinout configuration and assignments are the same of the GRSD that is fully compilated and it works properly on Terasic board. Somebody can help me, please?