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Fitter can't route 4th PLL to 4th DDR3 controller in EP4SGX70

Altera_Forum
Honored Contributor II
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Fitter can't route 4th PLL to 4th DDR3 controller in EP4SGX70. 

 

Four autonomous NIOS components each with a uniphy DDR3 controller in qsys. The Fitter can't connect the last NIOS component's DDR3 controller to the last PLL. 

 

Too much DDR3 memory for one NIOS but could use 2 NIOS modules each with 2 DDR3s that share a PLL, master --> slave. One early design iteration was set up that way on an earlier release of Quartus. It required manual editing of some ddr3 files in the synthesis/modules directory for sharing the PLL. Don't know if that's still necessary with Q11.1. 

 

If it's possible to manually place or assign the PLL to each qsys component I could try to find a mapping that compiles okay.
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