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Fitting a clock on a CycloneIV GX device with 115K Elements

Altera_Forum
Honored Contributor II
811 Views

Good morning, 

 

As I'm not sure where to post this topic, I submit it here. 

 

I am currently developping on a CycloneIV_GX115. The manually crafted VHDL code works fine as far as I can see. However, in order to implement some functions, I have tried to switch the design to a NIOS_II processor which uses 32K M9K RAM plus a 128K ROM. 

 

With the NIOS II processor, the clocks that were previously fitting on the hard coded VHDL don't anymore. I get a message from the fitter with the input PLL I have put on the primary clock : 

 

error (176559): can't place mpll or gpll pll "pll_64_to_40:pll_inst|altpll:altpll_component|pll_64_to_40_altpll:auto_generated|pll1" in pll location pll_6 because i/o cell "clock" cannot be placed in i/o pin pin_l11 (port type inclk of the pll) 

 

 

If I try to route the clock signal directly, I get from the fitter : 

 

 

error (170084): can't route signal "clock~input" to atom "clock~inputclkctrl" 

 

The device is an ep4cgx110df31c7. I am using a clock (processor clock) on pin L11, single ended. I am also using a GXB clock differential LVDS on pins K15/L15 (this one fits), for GXB using differential pins AB4/3 and AC2/1. I konw that this clock isn't the dedicated clock for the corresponding GXB, but it is routed so on the board I was given, so I have to cope with it. 

 

Now, I have several hypothesis : 

- either the NIOS and the GXB routing is not possible (due to the RAM for instance) 

- or there is a problem with mismatching clocks from pins L11/L15 competing for the same resource (PLL6) 

 

Am I right thinking so ? Any help is welcome. Is there a way to use both clocks simultaneously with the NIOS design ? 

 

Kind Regards.
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