Hello,I am trying to write an application into the CFM Space in my Max10 (10M50DAF484C6 on the Development Kit board) made with NIOS2 SBT with the flash programmer and get the error 8. What i read in https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/ug/ug_nios2_flash_program... is that i need an additional Tristate Conduit Bridge and EPCS Serial Flash Controller (Table 1-1) but in QSYS the Flash Controller component is not supported for this FPGA. I have a Qsys System with: Clock Source, System ID Peripheral, JTAG UART, NIOS2 Processor (f), On-Chip Memory (RAM), Altera Dual Configuration, Altera On_chip Flash, Uart (RS-232 Serial Port) and PIO outgoing. Edit: I am able to put the application into the UFM space with Memory Initialisation in QSYS. To explain why i want to do this. The Image in CFM0 is just for RSU and uses not much space so i thought it would be a good way to save the application into to remaining space of CFM0 My second thought was to edit the .pof file i use for programming. It is in Intel-format and when i build mem_init_generate i get the .hex files which i can convert to intel-format and put them into the .pof file. My third guess was to write a programm which writes into flash. The first method sounds like the most stable and simple for me. Does someone has a solution to this error and/or an other way to approach my desired result?
Thank you for your reply,I had a look at the .pdf but what i am missing is the option to write the application into CFM. Executing from UFM is working for me but i want to operate without external memory components and execute in the CFM Also i would prefer to write my design with one click into the fpga. I would like to avoid writing an application which copies the data into the CFM. For the flow to program EPCS, i am using internal configuration for the dual-image. Do free to correct me if i am missing something here. Edit: Sorry, i forgot that the flash programmer uses EPCS. I write again when i tried the link. Edit2: EPCS/EPCQ controller is not supported with max10. Ok so i can use this with other FPGA's. Do you have a solution for max10 devices?