Flash Programmer Question

[Altera_Forum]

Can anybody explain to me does Altera Flash Programmer places boot loader automatically before main programm at flash for copying main program to sdram or not? 

Or I must write my own boot loader and then tell Flash Programmer to program it before my main program?

[Altera_Forum]

The flash programmer does indeed place a bootloader in flash to copy your code out to RAM

[Altera_Forum]

--- Quote Start ---  originally posted by rugbybloke@Dec 2 2004, 10:12 AM the flash programmer does indeed place a bootloader in flash to copy your code out to ram  --- Quote End ---   Hi,  Currently we use the Flash programming Tool to program our custom board (under development). In the operational phase we will not have the JTAG to program the flash. So we will have to download the FPGA codes and our application onto the RAM and then reprogram the entire EPCS flash (thus probably including  the bootloader).  Do you know if there is documentation about how we can can do this? Maybe you have other tips.  Thanks in advance.  Regards,  Kwok Kwok

[Altera_Forum]

kwokwong 

 <div class='quotetop'>QUOTE </div>  --- Quote Start ---  So we will have to download the FPGA codes and our application onto the RAM and then reprogram the entire EPCS flash (thus probably including  the bootloader).[/b]  --- Quote End ---    May be you can use remote system update feature?  You need to add to your design any kind of communication with external world (uart or ethernet for example). And than add feature to your programm to write flash at specified address with data recieved via communication interface. In this way, as I understand, you will need to write your own bootloader if you wish to programm flash with code footprint beginning at address 0x00000000. So firstly you programm your bootloader and then you programm your code. In other hand may be you will be able to find how much space occupies Altera Flash Programmer bootloader and write your code footprint right after it. If you discover end address of Altera Flash Programmer bootloader Please post it here - it will be wery usefull to know this. Info about remote update can be found on Altera web server. This feature is applicable to EPC devices too.

[Altera_Forum]

--- Quote Start ---  originally posted by macshiz@Dec 3 2004, 04:13 AM kwokwong[/b]  <div class='quotetop'>QUOTE   --- Quote End ---    --- Quote Start ---  So we will have to download the FPGA codes and our application onto the RAM and then reprogram the entire EPCS flash (thus probably including  the bootloader).[/b]  --- Quote End ---    May be you can use remote system update feature?  You need to add to your design any kind of communication with external world (uart or ethernet for example). And than add feature to your programm to write flash at specified address with data recieved via communication interface. In this way, as I understand, you will need to write your own bootloader if you wish to programm flash with code footprint beginning at address 0x00000000. So firstly you programm your bootloader and then you programm your code. In other hand may be you will be able to find how much space occupies Altera Flash Programmer bootloader and write your code footprint right after it. If you discover end address of Altera Flash Programmer bootloader Please post it here - it will be wery usefull to know this. Info about remote update can be found on Altera web server. This feature is applicable to EPC devices too. [/b]  --- Quote End ---   So far I figure out: 1. You can use elf2flash utility to add the bootloader (boot_loader_epcs.srec) to your own application (output: epcs_controller_boot_rom.flash). 2. You can use sof2flash utility to convert the FPGA to a .flash file (epcs.flash) 3. You can use the HAL EPCS flash api to program the flash .  What I DON&#39;T know: 1. To where (flash address) should I write the flash content? Or can I just follow the addresses in the SREC&#39;s?

[Altera_Forum]

--- Quote Start ---  originally posted by macshiz@Dec 3 2004, 04:13 AM kwokwong[/b]  <div class='quotetop'>QUOTE   --- Quote End ---    --- Quote Start ---  So we will have to download the FPGA codes and our application onto the RAM and then reprogram the entire EPCS flash (thus probably including  the bootloader).[/b]  --- Quote End ---    May be you can use remote system update feature?  You need to add to your design any kind of communication with external world (uart or ethernet for example). And than add feature to your programm to write flash at specified address with data recieved via communication interface. In this way, as I understand, you will need to write your own bootloader if you wish to programm flash with code footprint beginning at address 0x00000000. So firstly you programm your bootloader and then you programm your code. In other hand may be you will be able to find how much space occupies Altera Flash Programmer bootloader and write your code footprint right after it. If you discover end address of Altera Flash Programmer bootloader Please post it here - it will be wery usefull to know this. Info about remote update can be found on Altera web server. This feature is applicable to EPC devices too. [/b]  --- Quote End ---   So far I figure out: 1. You can use elf2flash utility to add the bootloader (boot_loader_epcs.srec) to your own application (output: epcs_controller_boot_rom.flash). 2. You can use sof2flash utility to convert the FPGA to a .flash file (epcs.flash) 3. You can use the HAL EPCS flash api to program the flash .  What I DON&#39;T know: 1. To where (flash address) should I write the flash content? Or can I just follow the addresses in the SREC&#39;s?

[Altera_Forum]

I have a similar problem. 

In my design a small initialization software is implemented in EPCS and loaded at power on via boot loader. After initialization of all ports and interfaces the programme starts a endless loop in internal RAM while system ram is mapped into PCI space (with shared access from local). From PCI side a new firmware will then be loaded. In the endless loop the processor detects, if reset address at offset 0 is not equal zero and jumps to the new reset start vector. I think this pocedure can be done if the content of the .flash file generated by NIOS II IDE is known. This file is based on the SREC format but differs. The first (S0) record contains in its address field a reference designator of the appropriate flash device (EPCS). The following S3 records contain code but not exactly correlated to the address fields. The last data word is the start address itself and is not stored in a S9-record as specified by motorola. Does anybody have a specification of the .flash file format? If this content is clear it should be no problem, to make a firmware update on-the-fly via any interface to externals.

[Altera_Forum]

<div class='quotetop'>QUOTE </div> 

--- Quote Start ---  What I DON&#39;T know: 1. To where (flash address) should I write the flash content? Or can I just follow the addresses in the SREC&#39;s?[/b]  --- Quote End ---    May be this will be usefull for you I found this docs and example about remote update on Altera Site. Example deals with EPCS device as i understand  http://www.altera.com/literature/hb/stx/ch...ence_design.zip (http://www.altera.com/literature/hb/stx/ch15_reference_design.zip) Also I have 10Meg arch named NiosII_BootCamp.zip I don&#39;t remember where I have got it. But it is also Altera produced documentation contains info about remote update features.

[Altera_Forum]

Found another problem. 

OK. I have Nios Stratix 1s10 dev board. Configuration scheme is one with MAX device. In such scheme configuration is stored in flash device. I have software to download any file to flash at desired location. So my question is: I produce .flash file with configuration by sof2flash utility. What I must write to flash? .flash file is in motorola srec format so I must write only data fields at specified addresses or I must write entire .flash file with all fields?

[Altera_Forum]

The .flash file should contain initialisation data for only part of the flash. The SREC address records describe offsets from the start of the flash chip. If you write the .flash file to flash using the flash programmer then the contents of locations not described in the .flash file should remain unchanged. 

 So your software should do the same, if an address is mentioned in the SREC file then write the appropriate data there, if it&#39;s not mentioned then leave it unchanged.

[Altera_Forum]

.flash file is not a standard SREC file! 

I&#39;ve realized a secondary bootloader that transfers "epcs_controller_boot_rom.flash" to the nios system ram via PCI-bus. In my design, reset vector is set to epcs-device and exception vector is assigned to system ram. I&#39;ve figured out that the address field of this .flash file is only a counter which has nothing to do with a storage address. The start address of the different sections are part of the srec data fields. A .flash S3 record starts with a size indicator (two characters just behind "S3") followed by a 8 character number in big endian format (a counter). The following data fields are organized as 8 character of 32bit data words in little endian format. The first Data word is a length indicator, the second data word is the target address. the rest are data words to be placed at target address. The length indicator counts bytes. Every line is terminated with a two character checksum as usual in SREC files. In my design the first data block consists of 12 Bytes (0x0C000000 in little endian) to be placed at address 0x00000000 (the reset start address). The next data block has 68612 Bytes (0x040C0100 in little endian) and has to be stored at address 0x00100020 which is the exception start vector in system ram. The third block in the .flash file has a length of 0 and an address that is the start address of the .text segment e.g. the start of the firmware. The boot loader is only added when &#39;FLASH PROGRAMMER&#39; is launched. This program generates a new .flash file, named as specified in the custom board design and obviously consists of Bootloader, Firmware and FPGA-Bitstream. I did not figure out how this file is organized.

[Altera_Forum]

Hm, may be you know what raw binary file (.rbf) contains? You can produce .rbf file from QuartusII File Menu->Convert Programming FIles. 

Is it that file I can write directly to user hardware image location (0x0060000) at flash for remote update of my system?

[Altera_Forum]

i have a little workaround to get a valid EPCS file for updating boards out in the field.  

 I use my board at the lab, which is equipped with a jtag connector and a RS232 port, program it, using the NIOS 2 IDE flash-programmer. Then i wrote a little c-program, which dumps the EPCS content to the RS232 port. I simply use the run feature of the IDE to transfer it to the target, overwriting the main application in ram. A terminal program is used to save the output, which is formated as iHex file, in a file.   Thats it - it is not perfect, but it works for me...

[Altera_Forum]

--- Quote Start ---  originally posted by macshiz@Dec 7 2004, 03:05 AM hm, may be you know what raw binary file (.rbf) contains? you can produce .rbf file from quartusii file menu->convert programming files. is it that file i can write directly to user hardware image location (0x0060000) at flash for remote update of my system?  --- Quote End ---   I&#39;m not sure if I understand you right. The .rbf file is one of several alternatives to store the data generated by quartus to make a FPGA working. I use this type of file when I initialize a blank FPGA via microcontroller. These databytes are transfered 1:1 to FPGA when it is in configuration mode. If you want to use a parallel flash you need an additional configuration controller to select and serialize this data (cyclone series) on power up. Besides configuration data, you need firmware to run a NIOS. This firmware must be loaded to RAM after FPGA configuration is done. A bootloader manages this step. Configuration data, bootloader and firmware can be merged together and stored for example, in a serial Flash (EPCS). This is build by quartus flash programmer together with a custom design and described in &#39;ug_nios2_flash_programmer.pdf&#39;.  Mike

[Altera_Forum]

mir 

 <div class='quotetop'>QUOTE </div>  --- Quote Start ---  The .rbf file is one of several alternatives to store the data generated by quartus to make a FPGA working. I use this type of file when I initialize a blank FPGA via microcontroller. These databytes are transfered 1:1 to FPGA when it is in configuration mode[/b]  --- Quote End ---    Thanks. This is that I want to know.

[Altera_Forum]

MiR, 

 The .flash file should be a standard .SREC file, and looks like one to me. See the boot-loader sources in components/altera_nios2/sdk/src/boot_loader_sources, particularly the comments in the .S file.  When I build a flash for use with a parallel (CFI) flash chip then my .flash file contains a bootloader followed by the data blocks for the bootloader to write into memory. Each of these consists of length, address, data as you suggest.  For EPCS the bootloader is stored in an on-chip ROM so the .flash file here should contain a set of data blocks, each containing length, address, data. This sounds like what you&#39;ve got. This data stream needs to be added on to the end of the data stream for the .sof file, becaue the bootloader (within the .S file) starts reading the data blocks from here. It sounds as though elf2flash is starting from offset 0 because it doesn&#39;t know the real start address where the data blocks should be stored.  If you can work out how big the device configuration data is then you should be able to add the offset manually and merge the files using objcopy. I know this isn&#39;t ideal but it may be easier than writing your own boot loader.

[Altera_Forum]

--- Quote Start ---  originally posted by macshiz@Dec 8 2004, 03:27 AM MiR[/b]  <div class='quotetop'>QUOTE   --- Quote End ---    --- Quote Start ---  The .rbf file is one of several alternatives to store the data generated by quartus to make a FPGA working. I use this type of file when I initialize a blank FPGA via microcontroller. These databytes are transfered 1:1 to FPGA when it is in configuration mode[/b]  --- Quote End ---    Thanks. This is that I want to know.[/b]  --- Quote End ---   You can use menu:  &#39;Assignments->Device->Device & Pin Options->Programming Files&#39;  to select several file types you want to be generated.  Mike

[Altera_Forum]

--- Quote Start ---  originally posted by wombat@Dec 8 2004, 06:00 AM mir, ....... for epcs the bootloader is stored in an on-chip rom so the .flash file here should contain a set of data blocks, each containing length, address, data.  this sounds like what you&#39;ve got.  .......  --- Quote End ---   There is obviously a difference in .flash files generated by NIOS IDE after linking to .elf (" ... Post-processing to create epcs_controller_boot_rom.flash ") and .flash files generated by the Flash Programmer.  Mike

[Altera_Forum]

--- Quote Start ---  originally posted by wombat@Dec 8 2004, 06:00 AM mir,  the .flash file should be a standard .srec file, and looks like one to me.  see the boot-loader sources in components/altera_nios2/sdk/src/boot_loader_sources, particularly the comments in the .s file.  --- Quote End ---   Hi wombat,  thanks for your interest in my issue. Meanwhile I agree with you that .flash files are SREC files. My problem arose from comparing the .flash file produced by GUI flash programmer and the patterns I&#39;ve got when reading the EPCS content in the running application.  Reading EPCS results in several 0xFFs followed by 0x56. A dump of the EPCS .flash file showed 0x6A as the first non FF byte. The miracle is: reading EPCS data shows content in reverse bit order: 0x56 = %01010110 0x6A = %01101010 ((reading is done by &#39;alt_read_flash()&#39;)  regards Mike