Hello,I'm trying to Frame Lock one CVI, to 2 CVOs. To achieve this, I gave the sof and sof_locked from the CVI, to the inputs of the CVO (in the .bdf File). The CVI control register bits 0 and 3 are set to 1. (0 to output the video, 1 to output the sof and sof_locked). Then I put the CVOs control registers bit 0, 3 and 4 to 1. (0 to output the video, 3 to output the own sof and 4 to synchronize the CVO sof to the CVO sof). Currently I get the pictures at my output, but they are not Frame Locked. So I think that I don't have correctly written the registers. Can you check it for me please? IOWR_32DIRECT(CVI_BASE, 0x0, 9); //d9 => b1001 IOWR_32DIRECT(CVO0_BASE, 0x0, 25); //d25 => b11001 IOWR_32DIRECT(CVO1_BASE, 0x0, 25); The base addresses seems to be right, because I get an output. IORD_32DIRECT(CVO0_BASE, 0x0); give out a "25". So it seems that it only read the first 16bit (the control register), but not the next 16 bit (status register), because if it would read the status register, it would be higher then 2^16 because the first bit of the status register should say me if the output is enabled, and actually it is. Can you help me with the addresses? Thank you, TI30X
--- Quote Start --- The component should have all addresses defined in system.h. Use them instead of writing to BASE address. --- Quote End --- Yes, I have CVI_BASE 0x10000800 CVO0_BASE 0x10009000 CVO1_BASE 0x10004000 IOWR_32DIRECT(0x10000800, 0x0, 9); //d9 => b1001 IOWR_32DIRECT(0x10009000, 0x0, 25); //d25 => b11001 IOWR_32DIRECT(0x10004000, 0x0, 25); I got the same result with this.
--- Quote Start --- Somewhere in headers there should be define of CVO0_STATUS_BASE, CVO0_CONTROL_BASE or something like that... --- Quote End --- In system.h, I have only CVO0_BASE, CVO0_IRQ, CVO0_NAME and so on, there is no CVO0_CONTROL_BASE.
Ok, we got it by usingIOWR(BASE, OFFSET, VALUE); for writing and IORD(BASE, OFFSET, VALUE); for reading. So the output of the status register is 1 and the videos are outputed (this is ok) but they are still not Frame Locked. Can it be, that my sof signals are wrong wired? I posted a pic about it. (SOPC-Picture cuted in the middle because of image size) https://www.alteraforum.com/forum/attachment.php?attachmentid=6654 Thank you!
I'm curious if there has been any resolution to this problem. I'm having the same issue. Everything is hooked up as described in the documentation and the register bits are set correctly (read/written via the system_console). The video still runs but is not locked to the input.
--- Quote Start --- I'm curious if there has been any resolution to this problem. I'm having the same issue. Everything is hooked up as described in the documentation and the register bits are set correctly (read/written via the system_console). The video still runs but is not locked to the input. --- Quote End --- Hi eliljey, I had not solved my problem. But I don't work further on with frame locking, because it is not the technic which I need. If you want to do frame locking, you have to use the same input and output video frequency. For example, you can't use the 91MHz clock from the video input and use a pll generated 91MHz clock for the output. As far as I know, this both clocks must be exactly the same. Greetings from Germany