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Altera_Forum
Honored Contributor I
870 Views

Gate level simulation Custom Instruction

Hello, 

 

I have this problem:  

I have developed a multicycle custom instruction in vhdl. I have done an RTL simulation in modelsim and all works fine (I simulate the custom instruction only, without the Nios II soft-core).  

Moreover, I have added the custom instruction to the Nios II soft-core with Nios wizard, and after the compilation i have used my custom instruction in the software using the Macro generated automatically, and all works fine.  

The problem is that i need to do also a gate level functional simulation and, when i try to do that for the only custom instruction re-using the same testbench stimulus of the RTL simulation, the custom instruction behaviour changes. 

Is gate level simulation possible to do for the only custion instruction?  

If yes, there are some particular synthesis setting for quartus? 

My doubt is that when the custom instruction is added to the Nios in the Nios wizard, automatically the vhdl file are synthesized in a particular way... 

Anyone can help me?
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3 Replies
Altera_Forum
Honored Contributor I
39 Views

does the custom instruction follow good design practice? it is it all combinatorial? why not post the code here so we can have a look?

Altera_Forum
Honored Contributor I
39 Views

I'm sorry but I can't post the code at the moment...what do you mean for good design practice? Separation of the sequential and combinatorial process, etc...I have suspected that the problem could be this, but why It works once loaded the system on fpga?

Altera_Forum
Honored Contributor I
39 Views

Another question: Does the nios processor reset the custom instruction after every use? I mean, when I use the macro of my custom instruction in the code, is it possible that there is a reset operation at the start or at the end of the macro? 

Reading in the nios ii custom instruction guide seems that the answer is no...can anyone confirm this?
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