Hello Everybody,I have a Nios II /f that runs "Hello world" properly on a DE2-115 in Q16.0 using FPGA on chip memory. The system is as simple as possible, cpu, jtag, ram, sysid, it runs at 50mhz, no PLLs involved. If I add an Terrasic SRAM component (IP from golden ref design) and change the reset vectors to the SRAM I get: error executing 'nios2-bsp-generate-files --bsp-dir . --settings settings.bsp', unexpected return code 1. error message: severe: cpu "cpu" reset memory "sram" has no matching memory region.
ii do not understand this given: Reset vector in CPU points to SRAM.AVALON.SLAVE offset = 0x00..0 Exception vector in CPU points to SRAM.AVALON.SLAVE offset = 0x00..20 And sram base is 0x0000_0000 to 0x001F_0000 (cpu data master and cpu instruction master both connected) Any help appreciated to solve this issue or explain what is going on. Best Regards, JOHI.
As Johi says above, you need to edit the BSP. On the Linker Script tab various memory regions are defined. What you will probably find is that the reset region in the BSP is still pointing to the on-chip RAM.
Hello TCWORLD,Thank you for the clarification of my rather cryptic statement. However i am a bit stuck in the same area: Removing my FPGA based RAM and inserting Sram in its place in another test application i am working on i get: INFO: Tcl message: "No system timer device" WARNING: Tcl script "bsp-set-defaults.tcl " error: CPU "nios2_gen2_0" has no memories connected to its Avalon master(s) SEVERE: [Error] altera_hal_linkerx_generator: Required linker section mappings do not exist: "[.entry, .exceptions, .rodata, .rwdata, .text, .bss, .heap, .stack]" SEVERE: [Error] altera_hal_linkerx_generator: Required linker section mappings do not exist: "[.entry, .exceptions, .rodata, .rwdata, .text, .bss, .heap, .stack]" In this case i cannot modify the BSP because no project is generated in Eclipse. Can you give me a direction what to do in this case ? Am I doing something completely illegal with my configuration where there is only a DE2-115 SRAM and a CPU? Maybe I need to add some onchip ram so the sram controller can get initialized properly, but my knowledge does not go far enough for to know this. What makes me think in this direction is that the SRAM has no .s1 extension when i select it in the cpu reset vector box. The SDRAM and FPGA RAM do have this extension. Many thanks, Johi.
Update (this is what I think is behind my problem):- After analyzing with an XML viewer the SOPC file, I see that the catalog components that expose a Avalon instruction master interface of type 'S1' all end up with a linker memory region in the BSP editor. Those that do not (JTAG / debug mem / sram ...) do not get a linker memory region. XML: "nios2_gen2.instruction_master/sdram.s1" <endConnectionPoint> = S1 - Since my SRAM component does not expose an S1 interface, I assume it cannot be used correctly as Avalon instruction master. - I tried to add a memory device manually (BSP add memory device) and linker memory regions (reset region + sram region) and succeeded in mapping the .bss, .entry, .heap, .rodata, .stack and .text to the SRAM chip manually. However, this was of no use because the BSP editor would not generate an application with these settings because they did not correspond to the data in the .sopc. (reset and exception vector regions not ok). For the last problem I did not find a solution. - There are some references that explain that you need to set the isMemoryDevice = 1. This is done for the sram block by checking the "use as pixel buffer for video out" checkbox in the sram parameter settings in Qsys. However, this did not solve the problem. (found this by analyzing the Sram tcl file). Best Regards, Johi