hiI implement a top level system, which is a multiprocessor system, with Qsys then generate the top level system for making subsystem's .SOPC file, but it does not make that. I am so confused, how can i do this(making subsystem's .SOPC files)?
If you are creating the system in Qsys, you won't find SOPC files. The subsystem components will be Qsys files. If you have a Qsys system in your active Quartus project and you open Qsys, it should appear at the top of the Component Library window under Project-System.
hiI did every thing in the right flow as you mentioned. I design a hierarchical system in Qsys. In our design we have a "Top Level System" contains 3 subsystems, which each have one processor NiosII, JTAG, and "avalon memory map pipeline bridge". Cod memory of this processors define as "absolute" type, which is maped to a memory in the Top level system by "avalon memory map pipeline bridge ". But I still have problems as below: If we create a .sopcinfo file for a subsystem, and attempt to build a BSP based on that .sopcinfo file, when the BSP or application tries to refer to components in the top level, those references fail. I found this solution for my problem: "you must generate a .sopcinfo from the top-level system, and base the BSP on this .sopcinfo file." Unfortunately, I have only the .sopcinfo file of top-level system.(that means I do not have .sopcinfo file of subsystems!!!). Please help me in this problem. Thanks a lot.
Are you trying to create a bsp based on the subsystem sopcinfo files? I think you just need the bsp for the top level and make sure you have access to all the sopcinfo files.
I don't have a hierarchical project to look at but I would guess that when you create the project in the SBT, you choose the sopcinfo file for the top level and then the processor you'd like to link to the project. That way you can target different processors in the same design.
All of the CPUs should be showing up assuming you are generating the top level system which contains the CPUs below it or within it.There seems to be some confusion about what you need to generate. Think of this like verilog or VHDL, you compile a top level module and all the children are compiled too. The same goes for Qsys, if you generate the top level system then all of the children (and their children, and so on....) are generated as well.