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Altera_Forum
Honored Contributor I
730 Views

Golden Design Guidance

I'm attempting to re-create the golden hardware design for the "de0-nano-SoC" or "Atlas SoC". 

 

Out of the box the device will boot and perform all of the basic functions. I can even compile and run code on it.  

 

However, if I try to use the design as is within the path: 

DE0-Nano-SoC_v.1.0.7_SystemCD\Demonstrations\SoC_FPGA\DE0_NANO_SOC_GHRD 

 

Nothing works. I've regenerated both the .rbf and .dtb then updated the using mkimage on the existing "boot.script" to create a new boot.scr to point to the updated files.  

 

I am able to use mkimage to re-create the OEM "boot.scr" and still boot. 

 

My setup is ahead of rocketboards guides. Using the golden reference design included on the installation CD and building it using Altera / Quartus 15.0 + updates.  

 

My steps for the GHRD in the path above: 

* use QSYS to update / generate the soc_system.qsys. 

* run the .tcl script generated by QSYS including the sdram pin locations and settings. 

* re-compile everything within Quartus including the new system. 

 

Boot-up looks as though the FPGA is never configured. I don't know what else to look at except that a flashing LED test within the FPGA code never starts. 

 

If I program the .sof with the test LED code using a board that is "live" then the LED flashes. It's only when I try to boot and configure the FPGA that things are dead. 

 

This has to be a fundamental misunderstanding on my part.  

 

Thanks in advance for your help! 

-Jon
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Altera_Forum
Honored Contributor I
30 Views

Hi, did you try to download a version from the terasic web? I mean the cd content. it may contain updated cd content. Got 1.08 there. 

 

"http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&No=941&PartNo=4#soc"
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