Re: H2F Bridge EMIF Access

Altera_Forum · ‎10-02-2017

Hi,

I am using an Arria 10 ReFLEX Achilles dev kit that includes 2 DDR4 memories. The first DDR4 is used by the HPS and the second one I am trying to access from the HPS as well. To do this, I am using the HPS2FPGA bridge and an address span extender. The address span extender is a window of 512MB with 1 subwindow and the control register for the span extender is connected to the lightweight h2f bridge. I previously posted in SoC Dev Kits I believe and my problem was that the HPS was freezing when I was trying to write to the memory via hps2fpga bridge. I had some other peripherals connected so I have removed those to eliminate some elements that could possibly contribute to my problem. Now after compiling a few times and removing the other elements, it does not freeze when writing. However, my problem now is that when I write values, some values read back are incorrect. I have a little test program that writes X amount of values sequentially, then reads them, changes the window via the lw h2f bridge and writes X values and reads them through all 8 of my defined windows of 512MB. Then, it also does another read afterward that only reads the values and checks if they are the expected values. The values that are wrong seem to be the first 32 bytes. However, in different compiles where I slightly change something (for example, I added an LED that is assigned to the DDR4 calibration success / fail signal) the values that do not change are different. In this particular build, I cannot write the first 32 bytes as mentioned before, but in the past, I have had some compiles where everything seemed to work properly (even with all of my peripherals connected, these are usually just PIOs). However, if I changed something such as adding another PIO, it may or may not work. This problem has been really puzzling for me. I am fairly new to FPGAs and Linux in general and I tried to troubleshoot this issue. Any tips would be helpful.

At first, I thought it was a DDR4 timing problem because I was not meeting the timing requirements set by the ReFLEX reference design project that I based mine off of. Because of this, I changed it to be as simple as possible with only the address span extender and 2 memories connected to the HPS. When doing this, I do not receive a timing requirement not met message, but as mentioned before it still does not work as expected.

Between the freezing and the incorrect values, I cannot figure out what the problem is. As a note, I did not write a kernel module to write to the bridges; I am using mmap() and /dev/mem file descriptor to access the location.

Any tips, push in any direction (pretty lost right now), or help would be greatly appreciated.

Thank you!

Altera_Forum · ‎10-03-2017

Hi here is a small update,

I decided to remove the address span extender to see if that was actually the cause of my distress. It turns out that the EMIF connected to the bridge is not working properly. However, I did add the peripherals on and now it does not work; so the next step for me is to remove the peripherals and confirm the functionality of the DDR4 without it. Any tips on how to test the RAM functionality would be great. Right now I am just writing, then reading to see if I get the same value. The next thing I was thinking of is writing from HPS, then read it from the FPGA side and loop it back to the HPS using a bridge.

Altera_Forum · ‎11-02-2017

Hi limshutian,

Do check your pin mapping once,as I faced a issue in my write when there was pin mapping problem.

Are you able to access DDR4 from HPS now? In HPS i have a 128 bit data whereas my DDR4 is 512 bit. When I send 4 data from HPS, the data must be combined and stored in DDR4. When I read back from HPS, I have to get all 4 data. But I get only the last data.

Did you face this issue or how did you try writing data?

Altera_Forum · ‎11-02-2017

Hi VijeyShankar,

My data bus for my DDR4 is 32 bit and my HPS output is also 32 bit. I have no problems accessing the DDR4 now. What ended up being the problem with my project is there was a timing problem and my timing requirements for the DDR4 was not met. I fixed that by adding some pipelineing between the multiple masters I have accessig the DDR4. I wrote the data from the HPS by using /dev/mem and mmap to read and write data to the DDR4 using the hps2fpga bridge.