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12409 Discussions

HELP:how to remove these timing critical warning

Altera_Forum
Honored Contributor II
779 Views

I get some critical warnings for timing,when I make the TSE project. 

 

I want to implement a 150MHz nios II system of TSE transciever, 

 

and I almost finish the hardware of nios II with the DE4 board. 

 

but I get the critical warnings,how to solve it ,help me please.thank you so much 

.. 

 

 

I attach the quartus II archive file,Please help me as your convenience! 

 

the Qsys componets like: 

 

CPU--> 

-->onchip memory 

-->pipeline bridge 1----> cpu peripherals 

-->pipeline bridge 2----> IOs 

-->pipeline bridge 3----> ext_flash 

-->TSE_MAC 

-->SGDMA-tx/rx 

-->descriptor memory 

 

 

thanks again!!
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3 Replies
Altera_Forum
Honored Contributor II
94 Views

Look for the top failing paths report in Timequest to determine where you need to add more pipelining. 

A typical path that needs a pipeline bridge is the one between the Nios CPU masters (data and instruction) and the CPU's JTAG debug slave interface. 

Going over 100MHz on a Nios II system on a Cyclone FPGA is possible, but requires some patience...
Altera_Forum
Honored Contributor II
94 Views

first thanks for your help. 

 

yes I place a pipeline bridge between cpu and jtag. as : 

 

cpu <----->pipeline bridge <---->[jtag uart,sysid,timer,..] 

 

but these critical warning are for the TSE. so it is a little complicated 

 

and difficult to me. 

 

 

 

 

--- Quote Start ---  

Look for the top failing paths report in Timequest to determine where you need to add more pipelining. 

A typical path that needs a pipeline bridge is the one between the Nios CPU masters (data and instruction) and the CPU's JTAG debug slave interface. 

Going over 100MHz on a Nios II system on a Cyclone FPGA is possible, but requires some patience... 

--- Quote End ---  

Altera_Forum
Honored Contributor II
94 Views

You should look at the top failing paths instead. It is in the "Macros" category in Timequest. 

If the failing paths are inside the TSE itself, then there isn't a lot you can do, except decreasing the frequency. If it is between the TSE and something else, then there may be something you can do.
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