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ABary
Beginner
780 Views

HPS DDR3 assigments

I have a prototype board that uses a DDR3 SDRAM connected to HPS in Cyclone V device.

The board has a error, bank pins BA[0] and BA[2] are swapped. Is it the way to re-swap this outputs ?

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3 Replies
a_x_h_75
New Contributor III
36 Views

Unfortunately not.

 

Does your design use both BA[0] & BA[2]? Are both wired up? Or are you intending to use a memory part which doesn't use BA[2]? Dare I suggest that, if they're both wired up and you fit a suitable memory device, it''l just work... Queue barrage of things I've failed to think of. However, having a quick look at the command truth table there aren't any commands that rely on the wiring of BA. So, selecting bank 0 instead of 2 and vice versa should simply result in data being written to and read from different banks in the memory device.

 

Cheers,

Alex

ABary
Beginner
36 Views

Many thanks for replay. In PCB pin HPS_BA[0] from HPS is connected to pin DDR_BA[2] on DDR3 memory (2 chips of 256Mx16), pin HPS_BA[2] is connected to DDR_BA[0], pins for address bit [1] are connected correctly. This error was detected, because of DDR calibration failed during U-boot preloader start.

Datasheet of used memory devices shows that mode registers are selected by BA[1..0] just. I hope there is the way to swap this bits, maybe in u-boot sources, or, I know it's crazy, in HPS system verilog sources.

 

Regards,

Andrew

a_x_h_75
New Contributor III
36 Views

I'm afraid you're stuck. They can be swapped - a restriction of the Hard Processor System you're using. Unfortunately, the I/O is hard wired as well.

 

Cheers,

Alex

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