Nios® II Embedded Design Suite (EDS)
Support for Embedded Development Tools, Processors (SoCs and Nios® II processor), Embedded Development Suites (EDSs), Boot and Configuration, Operating Systems, C and C++
Announcements
Intel Support hours are Monday-Fridays, 8am-5pm PST, except Holidays. Thanks to our community members who provide support during our down time or before we get to your questions. We appreciate you!

Need Forum Guidance? Click here
Search our FPGA Knowledge Articles here.
12409 Discussions

HPS SPI Master with more than 4 Slave Selects

Altera_Forum
Honored Contributor II
1,098 Views

Good afternoon, 

 

for a new hardware project we require an SPI interface from an Arria 10 SoC with more than 4 slave devices / slave selects. 

The Arria 10 SoC SPI Master Controller does only support up to four slave selects according to the documentation though. 

 

What is a good way to support more than 4 slave selects?  

 

Any help is highly appriciated.  

 

Thanks!
0 Kudos
1 Reply
Altera_Forum
Honored Contributor II
126 Views

A 4->16 decoder with the 4 CS lines as input will allow you to access to 16 slaves. 

The 4 bits of the SER register are sent out (inverted) "as is" on the 4 chip selects lines 

 

SER register description: 

each bit in this register corresponds to a slave select line (spim_ss_x_n] from the spi master. when a bit in this register is set (1), the corresponding slave select line from the master is activated when a serial transfer begins. it should be noted that setting or clearing bits in this register have no effect on the corresponding slave select outputs until a transfer is started. before beginning a transfer, you should enable the bit in this register that corresponds to the slave device with which the master wants to communicate. when not operating in broadcast mode, only one bit in this field should be set. 

Reply