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Altera_Forum
Honored Contributor I
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Handling Incoming packet coming from PC(other source) to FPGA via TSE MAC

Hi, 

just need one idea for UDP Offload Example: 

(1) For outgoing Packet (FPGA to PC(other sink) via TSE MAC): I wrote the register of PRBS packet generator and UDP payload inserter like  

PRBS_PACKET_GENERATOR_WR_BYTE_COUNT(GENERATOR_0_BASE, 0x5be); 

UDP_PAYLOAD_INSERTER_WR_MAC_DST_HI (UDP_INSERTER_0_BASE, 0xe0db55d6 ); 

which is equivalent to writing IO as 

# define PRBS_PACKET_GENERATOR_WR_BYTE_COUNT(base, data) IOWR(base, 1, data) 

 

(2) But For incoming packet (PC (other source) to FPGA via TSE MAC): from which component I receive the incoming packet and from which Port/Pin and  

which register has to be read (set) via software like # define PRBS_PACKET_GENERATOR_RD_BYTE_COUNT(base) IORD(base, 1)?  

 

Regards
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