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[Hardware Testing]How to connect the jtag-MM in Top level. ref. [Low Latency Ethernet 10G MAC Intel Cyclone 10 GX FPGA IP Design Example User Guide]



I need some help. I want to know what is error and how to do it.

​Where should I check?

If anyone has ever run a demo board, please help me.


Thanks in advance


<Used cyclone 10gx DEV>

[Top file in sample project]

module altera_eth_top # (

    parameter NUM_CHANNELS = 2,

    parameter DEVICE_FAMILY = "Cyclone 10 GX"


  input  wire      csr_clk,

  output wire      core_clk_312,

  input  wire      ref_clk_clk, 

  input  wire      master_reset_n,

  output wire      sfp0_txdisable,

  output wire      sfp1_txdisable,

  output wire      xfp_txdisable,

  output wire [1:0]   SFPP0_RATE_SEL,

  output wire [1:0]   SFPP1_RATE_SEL,


  // LED

  output wire [NUM_CHANNELS-1:0]     block_lock_n,

  output wire [NUM_CHANNELS-1:0]     tx_ready_export_n,

  output wire [NUM_CHANNELS-1:0]     rx_ready_export_n,

  // debug clock

  output wire      core_clk_156,

  output wire [NUM_CHANNELS-1:0]     tx_serial_data,

  input  wire [NUM_CHANNELS-1:0]     rx_serial_data,

  output wire       core_pll_locked_n,

  output wire       atx_pll_locked_n,

  output wire [NUM_CHANNELS-1:0]    avalon_st_rxstatus_valid_156,

  output wire [NUM_CHANNELS-1:0][39:0] avalon_st_rxstatus_data_156,

  output wire [NUM_CHANNELS-1:0][6:0] avalon_st_rxstatus_error_156


wire              csr_rst_n;

wire              tx_rst_n; 

wire              rx_rst_n; 

wire [NUM_CHANNELS-1:0]     block_lock;

wire [NUM_CHANNELS-1:0]     tx_ready_export;

wire [NUM_CHANNELS-1:0]     rx_ready_export;

wire              core_pll_locked;

wire              atx_pll_locked;

assign csr_rst_n = master_reset_n;

assign tx_rst_n = master_reset_n;

assign rx_rst_n = master_reset_n; 

assign sfp0_txdisable = 1'b0;

assign sfp1_txdisable = 1'b0;

assign xfp_txdisable= 1'b0; 

assign SFPP0_RATE_SEL = 2'b11;

assign SFPP1_RATE_SEL = 2'b11;

assign block_lock_n = ~block_lock;

assign tx_ready_export_n = ~tx_ready_export;

assign rx_ready_export_n = ~rx_ready_export;

assign core_pll_locked_n = ~core_pll_locked;

assign atx_pll_locked_n = ~atx_pll_locked;

altera_eth_10g_mac_base_r #(



  ) dut_inst (

  .csr_clk      (csr_clk),

  .csr_rst_n     (csr_rst_n),

  .core_clk_312    (core_clk_312),

  .tx_rst_n      (tx_rst_n),

  .rx_rst_n      (rx_rst_n),

  .ref_clk_clk    (ref_clk_clk),

  .core_clk_156    (core_clk_156),

  // csr interface

  .csr_read      (1'b0),

  .csr_write     (1'b0),

  .csr_writedata   (32'b0),

  .csr_readdata    (),

  .csr_address    (16'b0),

  .csr_waitrequest  (),

  .tx_ready_export  (tx_ready_export),

  .rx_ready_export  (rx_ready_export),

  .block_lock     (block_lock),

  .tx_serial_data   (tx_serial_data),

  .rx_serial_data   (rx_serial_data),

  .core_pll_locked  (core_pll_locked),

  .atx_pll_locked   (atx_pll_locked),

  .avalon_st_rxstatus_valid_156      (avalon_st_rxstatus_valid_156),

  .avalon_st_rxstatus_data_156      (avalon_st_rxstatus_data_156),

  .avalon_st_rxstatus_error_156      (avalon_st_rxstatus_error_156)




[ To Interface the Jtag]

Add to Top file...........

wire           [31:0]   jtag_if_address;

wire              jtag_if_read;

wire             jtag_if_write;

wire           [31:0]   jtag_if_writedata;

wire           [31:0]   jtag_if_readdata;

wire                jtag_if_readdatavalid;

wire                jtag_if_waitrequest;

  // JTAG Master

  alt_jtag_csr_master jtag_master (

    .clk_clk              (csr_clk),

    .clk_reset_reset          (~reset_n),

    .master_address         (jtag_if_address),

    .master_write           (jtag_if_write),

    .master_read            (jtag_if_read),

    .master_writedata         (jtag_if_writedata),

    .master_readdata          (jtag_if_readdata),

    .master_readdatavalid       (jtag_if_readdatavalid),

    .master_waitrequest        (jtag_if_waitrequest)


After compiling, Run tcl in Tcl console

% pwd


% cd c:/intelFPGA_pro/SNS_Q102/hwtesting/system_console/

% pwd


% source loopback_conf.tcl



Info: Opened JTAG Master Service


Read loopback status

error: master_read_32: This transaction did not complete in 60 seconds. System Console is giving up.

  while executing

"master_read_32 $jtag_master $address_hex 1"

  (procedure "rd32" line 6)

  invoked from within

"rd32 [expr {$CHANNEL*0x10000 + 0xC000}] 0x800 0x00"

  (file "loopback_conf.tcl" line 25)

  invoked from within

"source loopback_conf.tcl"

Please. I need your help.

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1 Reply

Hi Asey,


I presume you are referring to Cyclone 10 GX 10G Ethernet example design from below link


If you are using Cyclone 10 dev kit board

  • Then make sure you configure the on board clock generator frequency correctly as per attached pic
  • JTAG master rely on on-board JTAG connection. You want to check to ensure your JTAG connection is working as well. You can use "jtagconfig" command to verify on board JTAG connection or run "jtagconfig --setparam 1 JtagClock 6M" command to reduce JTAG frequency to improve the signal quality
  • You are running Avalon-ST loopback via "source loopback_conf.tcl". This is the loopback where external Ethernet tester generate traffic to FPGA Eth RX pin, loopback internally inside FPGA and then re-transmit back to FPGA Eth tx pin then to Ethernet tester. So, you need to verify your tester setting as well


else if you are using your own board

  • Then make sure you configure all the FPGA pin assignment correctly and double check your board FPGA power, JTAG, clock and reset connection before you run the Ethernet testing