Honored Contributor II
02-06-2017 08:54 PM
Hello,I want to connect a hardware module implemented in Verilog with NiosII processor. The module has an output of 40 bits with an update rate of 500us. At the moment I have implemented the connection using IOs but the problem is that the processor reads the output register many times cause it runs faster and i don't know if the module has been updated or I read an older value. I really also want to avoid interrupts. I tried again by creating a counter in the module which increases by one every time the value is updated so I can discard the reading if the counter has the same value but I want something more general like a FIFO. What would be the best solution to my problem. I am thinking of ST-Avalon dual clock FIFO but I have no prior experience with that block, can anyone help me?