Help in CRC custom instructions please.

[Altera_Forum]

Hello, 

 I am a new bie in the custom instruction development for Altera and was looking into the way the CRC method is implemented as per the link altera.com/support/examples/nios2/exm-custom-instruction.html  I see the main C file which calls the custom instruction as crc_main.c and the custom instruction is crcCI. That function is defined in the file ci_crc.c. In that function, the macro CRC_CI_MACRO is called with the arguments. The macro is defined in the same file as:# define CRC_CI_MACRO(n, A) __builtin_custom_ini(ALT_CI_CRC_INST_N + (n & 0x7), (A))  The macro is being assigned to a built in gnu gcc custom function (if my understanding is correct). My questions are as follows:  Where can I see the gnu built in custom function (I mean, in which file). It should expand like a driver level function I guess. And where is the macro ALT_CI_CRC_INST_N being defined?  If all the custom gnu gcc functions are in-built, then how is it really a custom instruction?  I am struck at this point of thought, please give me some pointers. That would be a huge help.

[Altera_Forum]

Hello, 

 Can someone be of help to me in this please. I am looking for a simple SOPC builder component example. I looked in the forum, however could not find any. Do I need to start a new thread asking for the same? Kindly let me know.  Thank You, Akhil

[Altera_Forum]

I don't think there is any simpler example available from Altera. But basically you need to read the www.altera.com/literature/manual/mnl_avalon_spec.pdf]avalon (http:[url) specification[/url], mostly the part about the memory mapped slave interface. Then you can create your component with such an interface, and use the component creator in SOPC Builder or QSys to make the .tcl file for you. 

You don't actually need to create a sw.tcl file in most cases, but you will need to write some C to access your component. The IORD and IOWR macros can be used to read or write the different registers. There shouldn't be anything preventing you from using the example checksum component in a DE1 project with Nios II EDS, it should work just as is.

[Altera_Forum]

Hello Daixiwen, 

 Really appreciate for the inputs. I was thinking the checksum hardware accelerator was hardware dependent. I have read the readme.doc in the zip folder (which contains the entire package for the checksum) and ran through the usage instructions. It states the batch script accomplishes the following steps: - Hardware programming file (.sof) downloads to the board - Application and BSP make files generation - Software compiles - Software (.elf) downloads to the board - Terminal is opened What I thought was the first step will be dependent on the board (once I had some issues with the JTAG cable ID when I tried to download some example programs onto the altera DEI board).  I shall try the instructions from the NIOS II command shell and will update you.  Thank You, Akhil

[Altera_Forum]

The bash script itself is probably hardware dependent, indeed. You will probably have to do all those steps manually:[list][*]copy all the custom component files to your DE1 project (in a folder called "ip" in your main project folder, so that SOPC builder finds it automatically)[*]add the component to your SOPC project in SOPC builder[*]recompile the Quartus project[*]download the .sof file to the DE1 board[*]update/recreate your BSP in Nios II EDS[*]compile the software[*]run it[/list]

[Altera_Forum]

Hello Daixiwen, 

 Really appreciate the help. I did the connections in the SOPC builder as you asked me and I am attaching the screenshot here. I am getting an error (which I think I can understand) which states the dma master source port does not has a startpacket signal  of 1 bits where as the sink port has. I have checked the read_mashttps://www.alteraforum.com/forum/attachment.php?attachmentid=7000 ter.v and the hw_*.tcl file which has the interface for the signal. I dont understand why an error like this pops up.  Please help me in fixing this error.   Thank You, Akhil

[Altera_Forum]

Hello, 

 Eventually I was able to fix it. The DMA Read Master SOPC component had a parameter in the streaming options 'Packet Support Enable' which has to be checked so that it will create the interface ports in the read_master_hw.tcl file. Now the SOPC build is through.    Thank You, Akhil

[Altera_Forum]

Glad you found the solution. The error messages from SOPC builder aren't very explicit when you aren't used to them.

[Altera_Forum]

Yeah! I took a long time to fix those. Google search did not help much. 

Now I am able to build the application code for CRC HW in my NIOS II IDE, however issues pop up when I run the code.  Error: Attempting to start the checksum accelerator while it is busy... exiting  Is the error that I get while running the code.  I have tried to build an SOPC system that looks like the sopc system given in the CRC example, did the SOPC and the Quartus II build and then did the NIOS II IDE build.  I see in the application code that for the hardware checksum they are registering an ISR. Was wondering these will work or not if I do not have a proper SOPC system. As of now the code is getting issues while it calls the following function: write_to_add_len_ctrl_registers()  Thank You, Akhil

[Altera_Forum]

The busy error message is strange. Either the component isn't reset properly (do you have a correct reset signal fed to your SOPC component?) or the CPU is not reading the correct address. 

For the second point, see if the system.h file in the BSP defines the correct base address for your component (it should be a# define xxx_BASE where xxx is your component name) and that it is used correctly in the code. You can also use some SignalTap probes on the component's Avalon bus to check that it is accessed correctly.