Help using QuartusII

[Altera_Forum]

Hi all!!! I've a question that may be simple for someone of you... 

 Let&#39;s suppose that in Quartus II I have to merge 2 wire in a single bus:  in1------>|               |--------- out in2------>|  How can I do this in a graphical way??? I remember in Max Plus II it was simple, but I don&#39;t know how to do this in Quartus.... http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/dry.gif   For the moment I use this code:  LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY adaptBus IS     PORT     (  in1      : IN STD_LOGIC;  in2      : IN STD_LOGIC;  out      : OUT STD_LOGIC_VECTOR (1 DOWNTO 0)     ); END adaptBus; ARCHITECTURE SYN OF adaptBus IS BEGIN     out(0)  <= in1;     out(1)  <= in2;      END SYN;  Thanks, bye! http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/wink.gif

[Altera_Forum]

Hi Matteo, 

 I would do it like this: click for image (http://www.entner-electronics.com/images/nios_forum_wire.jpg)  Hope this helps...  Thomas www.entner-electronics.com (http://www.entner-electronics.com)  P.S.: After reading BadOmen&#39;s post, I added some more examples

[Altera_Forum]

Just like in the picture, by using the comma you are telling it to merge the signals left to right. So in1 maps to out[1], and in0 maps to out[0]. Another way if it makes things neater is by simply calling the single lines out[0] and out[1], after that if you refer to out[1..0] Quartus will already know to put those together as a bus. (Just like in the "C" language you can have an array but work with the individual elements one at a time) 

 That wire symbol in the picture means that you are taking one net name (in0 and in1) and giving it another name (out[0] and out[1]). This is so that Quartus doesn&#39;t flag it as an error (it&#39;s not a design error, but just how the design gets processed overall).

[Altera_Forum]

Thanks! 

 Bye http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif

[Altera_Forum]

Further on creative schematics: 

I have used the following output pin namings for 3 separate "output pin" instances in quartus schematics (5 physical pins in total in this example): outSignal outSignal2 outSignal and it almost works.  The compiler seems to generate the correct equations, but the assignments get confused:  You can not refer to the entire group using outSignal[4..0], and/or the Tcl reference for instance outSignal\ breaks,,, whichever catches you first. Anyway it apparently does not always work as expected, so maybe this is a little too creative after all.

[Altera_Forum]

Hi larsen, 

 I can remember that I had similar problems with assignments to pin-locations. I think I could solve it using outSignal[2] instead of outSignal2 http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/mad.gif . Maybe this also helps in your case.  BTW: I only use lower-case symbol-names, I think I read somewhere in the "Known Issues" section, that using upper-case in symbol-names can lead the some problems http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/unsure.gif .  Regards  Thomas  www.entner-electronics.com (http://www.entner-electronics.com)

[Altera_Forum]

Ok, thanks to all. 

 I have a 32 bit bus signal, but I need only two bits (LSB).  Does anybody know how to do that in a graphical way, without using vhdl?  in --------------- out where out0 = in0 out1 = in1   bye! http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/wink.gif

[Altera_Forum]

Hi Matteo, 

 leave the traces open on one side and assign bus with label. Quartus connects signals with same netnames :  in ---------------              ---------------in ------(Wire-Buffer)-----------out  That&#39;s the way I use it.  Mike

[Altera_Forum]

Or just do it directly: 

 in[31..0] ..... then when you need those bits just use a bus of in[1..0] If you want each signal separately, then you use in[1] and in[0] (or you can wire these to another alias).  That&#39;s the reason for naming signals (called aliasing), so that you can bring signals everywhere without having to directly connect them in your schematic (this is true with all good schematic software).  Use the wire component if you want to rename in[1..0] to something more descriptive if you need that (wire basically associates two net aliases together without causing an error).