Warning (12020): Port "jdo" on the entity instantiation of "the_led_nios2_gen2_0_cpu_nios2_oci_itrace" is connected to a signal of width 38. The formal width of the signal in the module is 16. The extra bits will be ignored.
I open file nios2_gen_cpu.v but it a asccii file . why it is a verilog file.
Thanks you very much
Can you please share with me a sample screen shoot of the Qsys connections? and how you connected it in the TOP level file?
Yes, the file is in Verilog to be compiled into the top-level for sure.