I have a program that's receiving data from an external source into a fifo that's 34 bits x 1024 words. I'm using the avalon fifo component from this forum for the low 32 bits, and a PIO for the top 2 bits. The PIO is used to signal the start/end of a data frame since the data in the low 32 bits could be anything. The program copies the data from the fifo into a packet and then sends it out over the network. I'm using a Stratix II dev kit with a NiosII/f processor, and running the micro-c RTOS.
The problem is that sometimes data comes into the fifo too quickly for my program to pull it out. I've streamlined the loop as much as I can (including taking out any printf's and the code that sends the ethernet packet for the time being) but the fifo still overflows sometimes. One thing I tried is moving .text, .rodata, and .rwdata into SRAM, and my heap and stack into the onchip RAM. This didn't seem to help. Is this the fastest setup possible? Does it make a difference what type of RAM I'm using for my fifo? Right now it's set to auto. Past that, what else should I be doing to make this run faster? How do I tell where the bottlenecks are?