I'm trying to make a shared memory region (with a mutex), but how do I access (from the HAL's perspective) a memory region outside my current subsystem?
the memory block will be located in the design top level.
If I understand your question correctly, you would like to have RAM (example) that you can access in your Nios subsystem & in your top level design.
There are multiple ways to do this;
One of them is to create a custom Nios component that contains a dual port RAM.
One side of the RAM can be accessed by your Nios configuration through the Avalon bus.
The other side of the RAM can be exposed by the component via an external component interface.
This interface is the link to your VHDL / Verilog code in your top level design.