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Valued Contributor III
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How important are System Design Contraint (*.sdc) files?

How important really is the SDC file? How important is it to eliminate all unconstrained paths? Does it have to be ALL of them? (such as altera_reserved_tdi and altera_reserved_tms that seem to work with JTAG) 

 

 

My experience has always been with simple designs, but now I'm building a 1Gbps in-line packet processor that intercepts and modifies Ethernet packets in real-time as they stream through. I noticed that I always fail timing in TimeQuest, and sometimes my design works, sometimes it doesn't. It's been driving me crazy for the last month. 

 

Client Computer ----> {Ethernet > FPGA > Ethernet} ----> Server
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Valued Contributor III
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Unconstrained JTAG I/O, ignore it. 

 

Timing violations in your processing path or critical I/O (GigE PHY, external memory), fix it. 

 

Usually the .sdc is what allows you to see problems through TimeQuest. Actually fixing the problems being flagged may require design changes. i.e. you can't fix the .sdc if your logic is unintentionally sampling data from the wrong clock.
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Valued Contributor III
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Ted,  

I was able to constrain my critical path, but like you said, I may have to change my design. I'm getting over 8ns slack on a 125Mhz clock (as seen in attached), but for some reason it will still work if I load the board a second time with the same *elf. Would this slack be overcome by either introducing additional clock sources (one per Ethernet interface) or using the "read latency" feature in Qsys component builder? I'm thinking the former would be a better. 

 

At any rate, thank you greatly. I went through the overview at altera timequest demo video (https://www.altera.com/education/demonstrations/timequest/timequest-demo.html) to get me started. It seems timing was definitely my issue. For those experience the same learning curve, intel altera timequest timing analyzer resource center (https://www.altera.com/support/support-resources/design-examples/design-software/timequest/sof-qts-t...) and the alterawiki timing constraints (http://www.alterawiki.com/wiki/timing_constraints) are great resources.
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Valued Contributor III
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I'm a newbie here, but I think sdc is very important when it comes to nios and ethernet. The tutorial with triple speed ethernet for de2-115 took a week because I didn't know about the timing constraint. >_<

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