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Altera_Forum
Honored Contributor I
950 Views

How to connect qsys clock output pin from PLL (C0 and C1) to two physical pin in MAX1

Hi all, 

 

 

I'm new to fpga. I got a BeMicro MAX10 and I'm using qsys and the eclipse tool to make a nios2 system. I'm using quartus ii web v15.02. I got a system that works: nios2, ocram, leds, timer. I just turn one or two LEDs in a pattern and move to the next after a second. As I said this works fine.  

 

 

Now I want to use the SDRAM on the board instead of the ocram. I read AN730 about booting options for nios in max10 devices so I'm using option 2 (UFM and external SDRAM). I made the nios2 system in qsys following a sample project from altera. I used the example SDRAM settings which was for the kit I'm using.  

 

 

Needless to say... it doesn't work. 

 

 

This thing has so many steps that it is very likely I messed up one or more so I figure I'll start by checking if C0 and C1 from the PLL are there and in the correct phase. So I have to connect the C0 to an external pin and internal to the rest of the system and C1 to the SDRAM clock pin and another external pin (I may have C0 and C1 backwards, sorry). But when I tried to assign the same output to two different pins in the pin planner it complaints that it is already used. 

 

 

Any help, comments or insights on how to proceed are welcome. 

 

 

Thanks
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4 Replies
Altera_Forum
Honored Contributor I
88 Views

Use a clock bridge. You input the pll clock and output an exported clock.

Altera_Forum
Honored Contributor I
88 Views

Yes, a clock bridge is used to bring a PLL generated clock out. 

 

Rather than trying to make a project based on an Altera project, I'd suggest taking a step back. Start with an SDRAM example project for your exact board. Verify the hardware by loading the already compiled output file. Once the hardware is known good, make sure you can build the project, without changes, from scratch. This will verify that you know how to build it. Make sure you can create working output files on your machine with the Quartus & eclipse versions you intend to use with the source files from the example. 

 

After doing all this, make small changes to the example, testing them one by one until it has what you need.
Altera_Forum
Honored Contributor I
88 Views

Yeah. That was the idea but I couldn't find a clean SDRAM example. The Altera web store shows a "Hello world" example with "off-chip memory" but it is mislabeled because it uses ocram instead. The one I'm using is the Nios full demo but it has a lot of stuff. I took my project that works and added the pll and sdram settings from the nios full demo. The problems is most of the demos and documents miss a few crucial steps and new me gets lost. It's a learning process, if it were too easy it would be boring :-). Thanks.

Altera_Forum
Honored Contributor I
88 Views

If the Nios full demo for your exact board is all you have that uses SDRAM, start with that. Get it going as I outlined above and then make mods. For now, always start with something that is known good even if it doesn't resemble what you want to end up with. By making small changes and verifying them, you slowly advance to where you want to be.

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