How to control "ready" signal of exported Av-ST using Nios II for simulation?
I'm trying to simulate the Frame Buffer II IP core with runtime control by Nios II on ModelSim. I create my system on Qsys and run the simulation through "Nios II Software Build Tools for Eclipse". The Frame Buffer II IP Core has an exported Avalon-ST that I want to simulate and observe its waveform. Since the exported Avalon-ST is not connected to anything, the ready signal holds the value x. How can I change this signal through Nios II software? When I simulated the Frame Buffer II without runtime control (and thus without Nios II), I ran the simulation through the testbench, which connected the exported avalon-ST to a avalon-ST sink BFM. I initialised and controlled the BFM through a verilog test file. I'm trying to do the same thing with the Nios II when running the simulation through eclipse, but I'm not sure how. I would appreciate any tips on this topic. Thanks in advance, Saeed