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How to design a Tristate Controller

Altera_Forum
Honored Contributor II
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Hi all, 

 

During the design of ethernet using EP4CE30 , I need to design a custom tristate controller which contains a avalon MM master and a tristate conduit master . The tristate conduit master will connect to a tristate conduit pin sharer. I want to get a example of tristate controller contain both avalon MM master and tristate conduit master.Can anyone help me? 

 

I also design a module as follow , bu t the name cannot be recognized by the tristate conduit master in qsys, and can not be seen in the tristate conduit pin sharer. why? 

 

 

// sram_m.v 

 

// This file was auto-generated as a prototype implementation of a module 

// created in component editor. It ties off all outputs to ground and 

// ignores all inputs. It needs to be edited to make it do something 

// useful. 

// 

// This file will not be automatically regenerated. You should check it in 

// to your version control system if you want to keep it. 

 

 

module sram_m ( 

input wire clk, // clock.clk 

input wire reset, // reset.reset 

 

//s0 interface 

 

input wire [20:0] s0_addr, // s0.address 

input wire s0_rdn, // .read 

input wire s0_oen, //output 

input wire s0_cen, //chipselect 

output wire [15:0] s0_rdata, // .readdata 

input wire s0_wrn, // .write 

input wire [31:0] s0_wdata, // .writedata 

input wire [1:0] s0_byten, //byteenable 

 

 

// tcm interface 

output wire [20:0] tcm0_address_out, // tcm0.addr 

output wire [15:0] tcm0_data_out, // tcm0.wdata 

input wire [15:0] tcm0_data_in, // tcm0.wdata 

output wire tcm0_chipselect_n_out, // tcm0.cen 

output wire tcm0_write_n_out, // tcm0.wrn 

output wire tcm0_read_n_out, // tcm0.rdn 

output wire [1:0] tcm0_byteenable_n_out, //byteenable 

output wire tcm0_data_outen, 

input wire tcm0_grant, // tcm0.grant 

output wire tcm0_request // .request 

); 

 

// TODO: Auto-generated HDL template 

 

 

 

assign s0_rdata = ((tcm0_grant==1) && (s0_rdn==0))? tcm0_data_in : 16'hzzzz; 

 

// assign tcm0_addr_out = (tcm0_grant==1 )? s0_addr : 16'hzzzz; 

 

// assign tcm0_wdata_out = ((tcm0_grant==1)&& ( s0_wrn ==0))? s0_wdata : 16'hzzzz; 

 

// assign tcm0_data_outen = ((tcm0_grant==1)&& ( s0_wrn ==0))? 1'b1 : 1'b0; 

 

// assign tcm0_cen_out = ((tcm0_grant==1))? s0_cen : 1'bz; 

 

// assign tcm0_request = s0_cen ? 1'b0 : 1'b1; 

 

endmodule
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