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Altera_Forum
Honored Contributor I
1,156 Views

How to disable RTOS?

Hi! 

Our Company is developing soft-processors using Nios I, but due to Nios I is not supported any more, as well as due to more advantageous JTAG use, we have to use Nios II. 

The problem we are facing is that certain requirements restrict use of interrupts, including RTOS. The issue is: Is there any possibility to create project without using RTOS, including HAL libraries? The best solution would be creating programs without using HAL functions, but JTAG-debug. In extremes, we would write Makefile by ourselves.
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14 Replies
Altera_Forum
Honored Contributor I
69 Views

If you are in the Eclipse IDE, you can still create a project without the RTOS. It will still compile the HAL though, but you don't have to use it if you don't want to. You can directly access the hardware from your application without using the HAL, and it won't be linked in. Making a custom Makefile to ensure it isn't even compiled is also a possibility, yes.

Altera_Forum
Honored Contributor I
69 Views

Thank you for your answer, but even if I use blank project with settings of "Hello world small" - size of the program is 4.5k. I think size of the blank program shoud be less than 1k. For our development, size is an important thing, because we also use several Nios-processors, based on 1 FPGA. 

I tried to compile blank program, something like this: 

void main() {}; //without any includes 

but HAL-libraries were included in Makefile, and size of program in .elf file isn't changed (4.5k). 

Can I exclude HAL from my project completely to minimize size of the program?
Altera_Forum
Honored Contributor I
69 Views

This starts to be a bit out of my field, and I hope someone else will be able to answer, but I think there are a few things that are done by the HAL before going into main(). 

If I remember correctly you can avoid those steps and begin in a function called alt_main() instead, with fewer initialization, but you will have to search a bit to see how this is done.
Altera_Forum
Honored Contributor I
69 Views

Did You enable -Os optimization? Optimization is disabled by default. 

Also You can run RTOS with only one task :) Well... rather more workaround than a logic solution.
Altera_Forum
Honored Contributor I
69 Views

And not a solution in this case, because even with only one task, the OS still uses the system timer and its interrupt to run the scheduler.

Altera_Forum
Honored Contributor I
69 Views

The only setup needed to get the niosII cpu running C code is to set the %sp and %gp registers. You might want to set %et (if you use interrupts). 

I set those directly in the linker script, then jump to my C code. 

 

With my own makefiles and linker script (I've posted chunks of it in the past) it is possible to get almost zero overhead. 

I run with pure code in tightly coupled instruction memory and all data (including .rodata) in tightly coupled data memory. 

Since we are a PCIe slave (to a ppc on the same pcb) download and diagnostic read of memory can be done without any of the altera boot schemes. 

 

The JTAG download can download such images - It seems to use the ELF program headers. 

The register set for the jtag uart is also defined, you can probably write small functions to write strings and integers to it. 

 

If you look at the code in alt_main() and main() (and the code that calls the former) you'll see a load of stuff to do with stdio and malloc. 

Particularly annoying is all the tidy up code!
Altera_Forum
Honored Contributor I
69 Views

Socrates, optimization decreases only size of the program, but doesn’t remove unnecessary libraries from the linker. And I would like to get pure Makefile. 

Daixiwen, exactly,and my aim is to control program work in full, and this can be achieved only at RTOS removal. Could you tell me how can I disable Makefile autogeneration? I can’t find the switch.  

dsl, thanks. I'll try to find your script. I think your method shall be ok
Altera_Forum
Honored Contributor I
69 Views

I don't use the IDE at all. 

Since I'm downloading using PCIe (we've exposed the nios soft-reset to the PCIe slave<->avalon bridge) I don't have any altera software installed at all. 

I use a copy of gcc (+binutils) built from the sourceson the altera ftp site and my own makefiles. 

The binary code+data for the nios is actually linked as binary data into a ppc linux program - this requires a system with both cross compilers installed! 

 

You do need to think of how you are going to get the code/data loaded in the field. Especially if you might want to do field upgrades. Anything of that nature is likely to be more friendly during development than having to rebuild the sopc image or download the code using jtag. Also best tested early!
Altera_Forum
Honored Contributor I
69 Views

dsl, thank you, but this method is not appropriate. I have a lot of ready boards having JTAG connectors. Moreover, official software must be used for certification. 

So, the issue is still open: how can HAL be taken away from Makefile? Maybe, shall I refuse BSP, but as far as I understand it is impossible?
Altera_Forum
Honored Contributor I
69 Views

If you intend loading the code as part of the fpga image, then how the binary data is generated for the M9K initialisation doesn't really matter. 

IIRC the binary data gets fed back into the latter stages of the creation of the fpga image. 

 

In any case none of the setup code is shipped in object format - so you can strip out all the unwanted junk. If you get the linker to generate a map file with all the cross-reference info it'll tell you why files get incuded from the .o libraries.
Altera_Forum
Honored Contributor I
69 Views

thank U, dsl! but i need to get into NIOS II IDE. If not, I'll have to use NIOS I.

Altera_Forum
Honored Contributor I
69 Views

I don't know of any reason why you can't do what you want using the IDE. 

I just have a massive aversion to the straightjacket that IDE put you into.
Altera_Forum
Honored Contributor I
69 Views

Hi Artyom, 

you can also take a look to objdump file (clearly previously enabled to be generated) just to understand what still remain in your application. 

Moreover you have also to remember that, all peripheral that you've foreseen in your FPGA design, automatically at compilation of BSP includes proper device driver: therefore 

if you don't want to use them you have to remove from you design or remove device driver within BSP editor. 

 

Ciao
Altera_Forum
Honored Contributor I
69 Views

Thank you everyone for your replies! Really, if not to use HAL functions, they won’t be included into the code (however, they are libraries in Makefile). And my code was big because of periphery drivers. I switched them off in BSP settings and got pure code (around 500 bites). That’s I wished to get. Thanks once again! I think the topic can be closed.

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