How to divide tasks to be done by Nios II processor & Logic elements?

[Altera_Forum]

Hi all, 

  I have a complete working project where I use MATLAB/Simulink with coding in S-function Level 2 as well as Simulink blocks.   Now I would like to convert the above project into C AND VHDL to be implemented on a hardware FPGA design on DE0 Nano Development board, Cyclone IV E. I am using Quartus II, SOPC builder, Nios II IDE or Altera monitor program.   In my Matlab project, basically what I was doing is to have thousand of inputs, sort them ascending/descending, do some comparison if-else, arithmetic operations, produce outputs, switching on/off devices. (I could give more details about this, the number of inputs/outputs could be reduced to the size permissible by hardware)     What I know: I am going to use BOTH the Nios II processor AND the logic elements on the development board, meaning I need to program Nios II using C language AND also program those logic elements using VHDL.    What I don't know: My question is, how do I determine which tasks are to be done by Nios II processor and which tasks are to be done by logic elements? Is there specific rule to follow or is it totally up to the programmer to decide? But I guess there should at least be some basic rules to adhere?     Forgive me if this really sounds stupid as I am really new to FPGA design as well as VHDL.   Hopefully someone could give me some inputs at least to get started. Thank you in advance.

[Altera_Forum]

Everything, that needs computing power, goes to the part with logic elements and VHDL, simple tasks like rs232 communication go to C code on Nios II.

[Altera_Forum]

How long is a piece of string? 

 Really it is balance between resource usage and processing speed. Code in C will typically be slower but use less resource than the same in VHDL. Very small blocks of VHDL can quickly perform operations that take quite a few code instructions.

[Altera_Forum]

--- Quote Start ---  Everything, that needs computing power, goes to the part with logic elements and VHDL, simple tasks like rs232 communication go to C code on Nios II.  --- Quote End ---    Thanks for your reply, linas... Correct me if I am wrong as I am really a beginner here, I thought I want the C code to do the tedious tasks instead of simple tasks cause VHDL tends to become very long for complicated task due to its low level language  sorting algorithm -  if-else comparison - switching on and off -   Can I assign the switching signals array in C language, then send one by one bit to the switching circuits represented in logic elements (VHDL)?  I think I still don't quite get the idea, sorry, do you mind to give me links/resources in order to learn how to determine/divide the workloads for Nios II processor (C language) and logic elements (VHDL)?  Appreciate your time

[Altera_Forum]

--- Quote Start ---  How long is a piece of string?  Really it is balance between resource usage and processing speed. Code in C will typically be slower but use less resource than the same in VHDL. Very small blocks of VHDL can quickly perform operations that take quite a few code instructions.  --- Quote End ---    Hi dsl, thanks for your reply... the coding (which I've previously done in Matlab/Simulink) is approximately 500 lines  Do you mind to give me links/resources in order to learn how to determine/divide the workloads for Nios II processor (C language) and logic elements (VHDL)?  I am curious how others determine the workload for Nios II processor (C language) and logic elements (VHDL)? or am I just the only one having this problem??

[Altera_Forum]

http://www.altera.com/literature/ds/ds_nios2_perf.pdf <- great document about performance of Nios II. As you can see, Nios II isn't performance leader. The question is simple: do you have the need for speed?

[Altera_Forum]

500 lines is a meaningless figure - it depends what the lines do. 

In particular what they require from any system libraries. My multi-channel hdlc engine is just over 1000 lines (500 contain a ';') and compiles to about 2k of object code (with no support libraries). The current version uses custom instructions to speed up the crc and bitstuffing and needs about 170 clocks per byte. A pure hdlc version would be must faster, but all the complex decision making is much easier in software.

[Altera_Forum]

The software in the nios is can be developed with less effort, but unfortunately the nios mostly can do only one thing at a time. In contrast the FPGA logic is really appropriate for parallel procesing, and pipelined processing (Avalon streams are frequently used to modularize the components).