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Yogesh
Novice
381 Views

How to load data to FPGA memory using NIOS application?

Hi,
I have developed some NIOS application, and I am using NIOS II Eclipse tool to run the same. Suppose I have some data in files. I want to load some amount of locations in DDR of my FPGA device with this data. I want to do this everytime I run the program as NIOS II hardware / everytime when I program the board .

1) I know that file read/write operations are slow in NIOS eclipse tool. It is only supported in debug mode .So I don't want to choose this option .
2) Is there anyway , so that I can load this data to DDR of my FPGA in " run mode " ?


Please provide some sample code / document for the same


Thankyou
Regards,
Yogesh
0 Kudos
7 Replies
Isaac_V_Intel
Employee
349 Views

Hello Yogesh,


You actually choose between debug or run mode on your toolbar.


Here is an example of a DRAM test on the following link [1], you are going to find the documentation at the same link. Next you are going to download the .par and create a project starting with this. This test is proved in Max 10 board.


[1] https://fpgacloud.intel.com/devstore/platform/16.0.0/Standard/sdram-nios-test-max10-de10-lite/


Best regards,

Isaac Vazquez.


Yogesh
Novice
346 Views

Hi Isaac,

The documentation link is not reachable.I am not able to access it.

And I did download the project , But I couldnt find the C codes to run on eclipse?

Am I missing something ?Please guide me.

 

 

regards,

Yogesh

Isaac_V_Intel
Employee
335 Views

Hi Yogesh,


You can find the documentation on the following link [1], next you need to find the SDRAM test in Nios ll.


Once you open the .par, you need to follow the steps and compile on eclipse, then at your project folder you are going to find a software folder, you can find the C code there.


[1] https://www.terasic.com.tw/cgi-bin/page/archive_download.pl?Language=English&No=1021&FID=a13a2782811...


Best regards.

Isaac


Yogesh
Novice
331 Views

Hi Isaac,

I dont have the DE -10 lite board to exceute the example design provided by you.

I am working with cyclone V GT board . That is why I want to understand the concept/ C code which writes the data to memory of FPGA. So that I can replicate the same in my C application.

I downloaded .par file and opened it in quartus . I could not find the software folder which contains the c codes required for eclipse. I have attached the screeshot of the files that are generated.

Please have a look into it and provide me the c code for the samepar_files.PNG

regards,

Yogesh

Isaac_V_Intel
Employee
318 Views

Hello Yogesh,

 

Yes, you need to follow these steps to get the C code.

 

  • Compile the Quartus project
  • Open Nios ll
  • Select the same Quartus project folder for the Eclipse project
  • Open Nios ll Aplication and BSP from Template and select the BSP that you have in your workspace
  • Compile the Nios ll project

 

If you follow these steps you are going to have the software folder and the C code. Also I attached the C code.

 

Best regards.

Isaac Vazquez

 

Yogesh
Novice
295 Views

Hi Isaac,

Thankyou for sharing the code.

I was able to write some data. But SDRAM_TEST fails at some addresses.

Say, If I try to write at addr 0x10005000 . I am able to write 3k bytes . But after that I am not able to write data, since SDRAM_test fails in that region.

I have shared BSP memory screenshot. Please answer my below queries:

1) SDRAM addressing has addr from 0x10000000 to 0x1fffffff . Does this mean I can write/read to all the address in this range ? 

2) Even if I change the address to 0x20000500, which is above that of SDRAM address range.  I am not able to write anything here. SDRAM_test fails . So , why am I not able to access this range of address?

3) Suppose I want addr from 0x20000000 - 0x2fffffff to store some initial input data for processing how should I specify in eclipse tool / qsys ,to access the same?

shot.PNG

regards,

Yogesh

Isaac_V_Intel
Employee
285 Views

Hello Yogesh,


Here are the answer to every single to your questions.


1) Yes, you can write at this section of the memory

2) Yes, the test fails because your accessible memory section is already defined. So, if you want to select other range or other section, you need to modify your platform design and rebuild the bsp.

3)Same, QSYS is related with platform designer.


Best regards,

Isaac Vazquez.


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